ZHCSR16 September   2022 TPS544C26

ADVANCE INFORMATION  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Internal VCC LDO and Using an External Bias on VCC/VDRV Pin
      2. 7.3.2  Input Undervoltage Lockout (UVLO)
        1. 7.3.2.1 Fixed VCC UVLO
        2. 7.3.2.2 Fixed VDRV UVLO
        3. 7.3.2.3 Programmable PVIN UVLO
        4. 7.3.2.4 Enable
      3. 7.3.3  Differential Remote Sense and Internal Feedback Divider
      4. 7.3.4  Set the Output Voltage and VID Table
      5. 7.3.5  Startup and Shutdown
      6. 7.3.6  Dynamic Voltage Slew Rate
      7. 7.3.7  Adaptive Voltage Positioning (Droop) and DC Load Line (DCLL)
      8. 7.3.8  Loop Compensation
      9. 7.3.9  Set Switching Frequency
      10. 7.3.10 Switching Node (SW)
      11. 7.3.11 Overcurrent Limit and Low-side Current Sense
      12. 7.3.12 Negative Overcurrent Limit
      13. 7.3.13 Zero-Crossing Detection
      14. 7.3.14 Input Overvoltage Protection
      15. 7.3.15 Output Overvoltage and Undervoltage Protection
      16. 7.3.16 Overtemperature Protection
      17. 7.3.17 VR Ready
      18. 7.3.18 Catastrophic Fault Alert: CAT_FAULT#
      19. 7.3.19 Telemetry
      20. 7.3.20 I2C Interface General Description
        1. 7.3.20.1 Setting the I2C Address
        2. 7.3.20.2 I2C Write Protection
        3. 7.3.20.3 I2C Registers With Special Handling
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forced Continuous-Conduction Mode
      2. 7.4.2 Auto-Skip Eco-mode™ Light Load Operation
    5. 7.5 Programming
      1. 7.5.1 Supported I2C Registers
      2. 7.5.2 Support of Intel SVID Interface
    6. 7.6 Register Maps
      1. 7.6.1  (01h) OPERATION
      2. 7.6.2  (02h) ON_OFF_CONFIG
      3. 7.6.3  (03h) CLEAR_FAULTS
      4. 7.6.4  (15h) STORE_USER_ALL
      5. 7.6.5  (16h) RESTORE_USER_ALL
      6. 7.6.6  (33h) FREQUENCY_SWITCH
      7. 7.6.7  (35h) VIN_ON
      8. 7.6.8  (36h) VIN_OFF
      9. 7.6.9  (40h) VOUT_OV_FAULT_LIMIT
      10. 7.6.10 (41h) VOUT_OV_FAULT_RESPONSE
      11. 7.6.11 (42h) VOUT_OV_WARN_LIMIT
      12. 7.6.12 (43h) VOUT_UV_WARN_LIMIT
      13. 7.6.13 (44h) VOUT_UV_FAULT_LIMIT
      14. 7.6.14 (45h) VOUT_UV_FAULT_RESPONSE
      15. 7.6.15 (46h) IOUT_OC_FAULT_LIMIT
      16. 7.6.16 (4Fh) OT_FAULT_LIMIT
      17. 7.6.17 (50h) OT_FAULT_RESPONSE
      18. 7.6.18 (51h) OT_WARN_LIMIT
      19. 7.6.19 (55h) VIN_OV_FAULT_LIMIT
      20. 7.6.20 (60h) TON_DELAY
      21. 7.6.21 (61h) TON_RISE
      22. 7.6.22 (64h) TOFF_DELAY
      23. 7.6.23 (65h) TOFF_FALL
      24. 7.6.24 (6Bh) PIN_OP_WARN_LIMIT
      25. 7.6.25 (7Ah) STATUS_VOUT
      26. 7.6.26 (7Bh) STATUS_IOUT
      27. 7.6.27 (7Ch) STATUS_INPUT
      28. 7.6.28 (7Dh) STATUS_TEMPERATURE
      29. 7.6.29 (80h) STATUS_MFR_SPECIFIC
      30. 7.6.30 (88h) READ_VIN
      31. 7.6.31 (89h) READ_IIN
      32. 7.6.32 (8Bh) READ_VOUT
      33. 7.6.33 (8Ch) READ_IOUT
      34. 7.6.34 (8Dh) READ_TEMPERATURE_1
      35. 7.6.35 (97h) READ_PIN
      36. 7.6.36 (A0h) SYS_CFG_USER1
      37. 7.6.37 (A2h) I2C_ADDR
      38. 7.6.38 (A3h) SVID_ADDR
      39. 7.6.39 (A4h) IMON_CAL
      40. 7.6.40 (A5h) IIN_CAL
      41. 7.6.41 (A6h) VOUT_CMD
      42. 7.6.42 (A7h) VID_SETTING
      43. 7.6.43 (A8h) I2C_OFFSET
      44. 7.6.44 (A9h) COMP1_MAIN
      45. 7.6.45 (AAh) COMP2_MAIN
      46. 7.6.46 (ABh) COMP1_ALT
      47. 7.6.47 (ACh) COMP2_ALT
      48. 7.6.48 (ADh) COMP3
      49. 7.6.49 (AFh) DVS_CFG
      50. 7.6.50 (B0h) DVID_OFFSET
      51. 7.6.51 (B1h) REG_LOCK
      52. 7.6.52 (B3h) PIN_SENSE_RES
      53. 7.6.53 (B4h) IOUT_NOC_LIMIT
      54. 7.6.54 (B5h) USER_DATA_01
      55. 7.6.55 (B6h) USER_DATA_02
      56. 7.6.56 (BAh) STATUS1_SVID
      57. 7.6.57 (BBh) STATUS2_SVID
      58. 7.6.58 (BCh) CAPABILITY
      59. 7.6.59 (BDh) EXT_CAPABILITY_VIDOMAX_H
      60. 7.6.60 (BEh) VIDOMAX_L
      61. 7.6.61 (C0h) ICC_MAX
      62. 7.6.62 (C1h) TEMP_MAX
      63. 7.6.63 (C2h) PROTOCOL_ID_SVID
      64. 7.6.64 (C6h) VENDOR_ID
      65. 7.6.65 (C8h) PRODUCT_ID
      66. 7.6.66 (C9h) PRODUCT_REV_ID
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Inductor Selection
        2. 8.2.3.2 Input Capacitor Selection
        3. 8.2.3.3 Output Capacitor Selection
        4. 8.2.3.4 VCC/VRDV Bypass Capacitor
        5. 8.2.3.5 BOOT Capacitor Selection
        6. 8.2.3.6 RSENSE Selection
        7. 8.2.3.7 VINSENP and VINSENN Capacitor Selection
        8. 8.2.3.8 VRRDY Pullup Resistor Selection
        9. 8.2.3.9 I2C Address Resistor Selection
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Performance on TPS544C26EVM
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 术语表
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information

封装选项

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订购信息

6.5 Electrical Characteristics

TJ = –40°C to +125°C; -40°C, 0°C, 25°C, 85°C, 125°C. PVIN = 4 V to 16 V, VVCC = 4.5 V to 5.0 V (unless otherwise noted). Typical values are at TJ = 25°C, PVIN = 12 V and VVCC = 4.5 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
PVIN operating input range 4 18 V
IQ(PVIN) PVIN quiescent current Non-switching, PVIN = 12 V, VEN = 0 V, no bias on VCC/VDRV pin 7.5 9 mA
IVCC VCC/VDRV external bias current 5 V external bias on VCC/VDRV pin, regular switching. TJ = 25°C, PVIN = 12 V, VOUT = 1.1 V, VEN = 2 V, fSW = 1 MHz 30 mA
IQ(VCC) VCC/VDRV quiescent current 5V external bias on VCC/VDRV pin, non-switching. PVIN = 12V, VEN = 2 V, VFB = VREF + 50 mV 5 mA
UVLO
PVINOV PVIN overvoltage rising threshold PVIN rising, VIN_OV_FAULT_LIMIT register (55h) = 0b 16.5 V
PVINOV PVIN overvoltage rising threshold PVIN rising, VIN_OV_FAULT_LIMIT register (55h) = 1b 18.5 V
PVINOV PVIN overvoltage falling threshold PVIN falling. PVIN_OVF status bit, once it is set, cannot be cleared unless PVIN falls below the PVIN overvoltage falling threshold
 13.5 V
VIN_ON PVIN turn-on voltage PVIN rising, VIN_ON register (35h) = 00b 10 V
VIN_ON PVIN turn-on voltage PVIN rising, VIN_ON register (35h) = 01b 9 V
VIN_ON PVIN turn-on voltage PVIN rising, VIN_ON register (35h) = 10b 8 V
VIN_ON PVIN turn-on voltage PVIN rising, VIN_ON register (35h) = 11b. Ignore VIN_ON setting, and use VCC UVLO rising threshold to enable the device. Disabled V
VIN_OFF PVIN turn-off voltage PVIN falling, VIN_OFF register (36h) = 000b reserved V
VIN_OFF PVIN turn-off voltage PVIN falling, VIN_OFF register (36h) = 000b 4.2 V
VIN_OFF PVIN turn-off voltage PVIN falling, VIN_OFF register (36h) = 001b 9.5 V
VIN_OFF PVIN turn-off voltage PVIN falling, VIN_OFF register (36h) = 010b 8.5 V
VIN_OFF PVIN turn-off voltage PVIN falling, VIN_OFF register (36h) = 011b 7.5 V
VIN_OFF PVIN turn-off voltage PVIN falling, VIN_OFF register (36h) = 100b 6.5 V
VIN_OFF PVIN turn-off voltage PVIN falling, VIN_OFF register (36h) = 101b 5.5 V
VIN_OFF PVIN turn-off voltage PVIN falling, VIN_OFF register (36h) = 110b 4.2 V
VIN_OFF PVIN turn-off voltage PVIN falling, VIN_OFF register (36h) = 111b.  Ignore VIN_OFF setting, and use VCC UVLO falling threshold to disable the device. Disabled V
PVINUVLO(R) PVIN UVLO rising threshold PVIN rising, 5V external bias on VCC/VDRV pin 2.0 2.55 3.0 V
PVINUVLO(F) PVIN UVLO falling threshold PVIN falling, 5V external bias on VCC/VDRV pin 1.8 2.3 2.8 V
PVINUVLO(H) PVIN UVLO hysteresis 0.25 V
ENABLE
VEN(R) EN voltage rising threshold EN rising, enable switching 1.14 1.19 1.24 V
VEN(F) EN voltage falling threshold EN falling, disable switching 0.94 0.98 1.02 V
VEN(H) EN voltage hysteresis 0.21 V
tEN(DIG) EN Deglitch Time 0.2 µs
EN internal pulldown resistor EN to AGND 87 103 119 kΩ
INTERNAL VCC LDO
tdelay(uvlo_I2C) Delay from VCC UVLO to I2C ready to communicate VCC/VDRV >= 3 V TBD ms
Internal VCC LDO output voltage PVIN = 4 V, IVCC(load) = 5 mA 3.925 3.97 4.0 V
Internal VCC LDO output voltage PVIN = 5 V to 16 V, IVCC(load) = 5 mA 4.28 4.44 4.55 V
VCC UVLO rising threshold VCC rising 3.69 3.75 3.81 V
VCC UVLO falling threshold VCC falling  3.49 3.55 3.61 V
VCC UVLO hysteresis 0.2 V
VCC LDO dropout voltage  PVIN – VVCC, PVIN = 4 V, IVCC(load) = 45 mA 90 144 226 mV
VCC LDO short-circuit current limit  PVIN = 5 V 150 200 mA
VOUT VOLTAGE
Output Voltage controlled through SVID interface Output voltage range by SetVID & SetWP commands 0.5 3.04 V
Output Voltage controlled through SVID interface Output voltage resolution by SetVID & SetWP commands 5 mV
Output Voltage controlled through SVID interface SVID fast slew rate, register (AFh) DVS_CFG = 010b 2.5 2.78 3.06 mV/µs
Output Voltage controlled through SVID interface SVID fast slew rate, register (AFh) DVS_CFG = 100b 5 5.5 6.1 mV/µs
Output Voltage controlled through SVID interface SVID fast slew rate, register (AFh) DVS_CFG = 110b 10 11.1 12.2 mV/µs
Output Voltage controlled through SVID interface SVID OFFSET range –127 127 Step
Output Voltage controlled through SVID interface SVID OFFSET resolution 1 Step
Output Voltage controlled through I2C interface Output voltage range by register (A6h) VOUT_CMD 0.5 3.04 V
Output Voltage controlled through I2C interface Output voltage resolution by register (A6h) VOUT_CMD 5 mV
Output Voltage controlled through I2C interface Output voltage transition slew rate by register (A6h) VOUT_CMD, register (AFh) DVS_CFG = 010b 0.625 mV/µs
Output Voltage controlled through I2C interface Output voltage transition slew rate by register (A6h) VOUT_CMD, register (AFh) DVS_CFG = 100b 1.25 mV/µs
Output Voltage controlled through I2C interface Output voltage transition slew rate by register (A6h) VOUT_CMD, register (AFh) DVS_CFG = 110b 2.5 mV/µs
Output Voltage controlled through I2C interface I2C offset (register (A8h) VID_OFFSET) range, 5mV VID step –63 63 mV
Output Voltage controlled through I2C interface I2C offset (register (A8h) VID_OFFSET) resolution, 5mV VID step 0.5 mV
Output Voltage controlled through I2C interface I2C offset (register (A8h) VID_OFFSET) range, 10mV VID step –127 127 mV
Output Voltage controlled through I2C interface I2C offset (register (A8h) VID_OFFSET) resolution, 10mV VID step 1.0 mV
VOUT(ACC) Output voltage accuracy TJ = 0°C to 85°C, VOUT = 0.75 V, VVOSNS–VGOSNS 0.744 0.75 0.756 V
VOUT(ACC) Output voltage accuracy TJ = 0°C to 85°C, VOUT = 1.1 V, VVOSNS–VGOSNS 1.0945 1.1 1.1055 V
VOUT(ACC) Output voltage accuracy TJ = 0°C to 85°C, VOUT = 1.8 V, VVOSNS–VGOSNS 1.791 1.8 1.809 V
VOUT(ACC) Output voltage accuracy TJ = –40°C to 125°C, VOUT = 0.75 V, VVOSNS–VGOSNS 0.7425 0.75 0.7575 V
VOUT(ACC) Output voltage accuracy TJ = –40°C to 125°C, VOUT = 1.1 V, VVOSNS–VGOSNS 1.089 1.1 1.111 V
VOUT(ACC) Output voltage accuracy TJ = –40°C to 125°C, VOUT = 1.8 V, VVOSNS–VGOSNS 1.782 1.8 1.818 V
IVOS VOSNS input current VVOSNS = 1.8 V 111 130 µA
SWITCHING FREQUENCY
fSW(FCCM) Switching frequency, FCCM operation TJ = –40°C to 125°C, PVIN = 12 V, VOUT = 1.1 V, no load, FREQUENCY_SWITCH register (33h) = 00b 540 600 660 kHz
fSW(FCCM) Switching frequency, FCCM operation TJ = –40°C to 125°C, PVIN = 12 V, VOUT = 1.1 V, no load, FREQUENCY_SWITCH register (33h) = 01b 720 800 880 kHz
fSW(FCCM) Switching frequency, FCCM operation TJ = –40°C to 125°C, PVIN = 12 V, VOUT = 1.1 V, no load, FREQUENCY_SWITCH register (33h) = 10b 900 1000 1100 kHz
fSW(FCCM) Switching frequency, FCCM operation TJ = –40°C to 125°C, PVIN = 12 V, VOUT = 1.1 V, no load, FREQUENCY_SWITCH register (33h) = 11b 1080 1200 1320 kHz
STARTUP
tON(DLY) Power on sequence delay VVCC = 4.5 V, register (60h) TON_DELAY = 00b 0.5 0.55 ms
tON(DLY) Power on sequence delay VVCC = 4.5 V, register (60h) TON_DELAY = 01b 1.0 1.1 ms
tON(DLY) Power on sequence delay VVCC = 4.5 V, register (60h) TON_DELAY = 10b 1.5 1.65 ms
tON(DLY) Power on sequence delay VVCC = 4.5 V, register (60h) TON_DELAY = 11b 2.0 2.2 ms
tOFF(DLY) Power off sequence delay VVCC = 4.5 V, register (64h) TOFF_DELAY = 00b 0 0.05 ms
tOFF(DLY) Power off sequence delay VVCC = 4.5 V, register (64h) TOFF_DELAY = 01b 1.0 1.1 ms
tOFF(DLY) Power off sequence delay VVCC = 4.5 V, register (64h) TOFF_DELAY = 10b 1.5 1.65 ms
tOFF(DLY) Power off sequence delay VVCC = 4.5 V, register (64h) TOFF_DELAY = 11b 2.0 2.2 ms
tON(Rise) Soft-start time VVCC = 4.5 V, register (61h) TON_RISE = 000b 1.0 1.1 ms
tON(Rise) Soft-start time VVCC = 4.5 V, register (61h) TON_RISE = 001b 2.0 2.2 ms
tON(Rise) Soft-start time VVCC = 4.5 V, register (61h) TON_RISE = 010b 4.0 4.4 ms
tON(Rise) Soft-start time VVCC = 4.5 V, register (61h) TON_RISE = 011b 8.0 8.8 ms
tON(Rise) Soft-start time VVCC = 4.5 V, register (61h) TON_RISE = 1xxb 16.0 17.6 ms
tOFF(Fall) Soft-stop slew rate, VOUT controlled by SVID VVCC = 4.5 V, register (65h) TOFF_FALL = 00b, Vboot = 1.1V, PROTOCOL ID = 07h, 5mV VID step 2.00 2.2 2.44 V/ms
tOFF(Fall) Soft-stop slew rate, VOUT controlled by SVID VVCC = 4.5 V, register (65h) TOFF_FALL = 01b, Vboot = 1.1V, PROTOCOL ID = 07h, 5mV VID step  1.00 1.1 1.22 V/ms
tOFF(Fall) Soft-stop slew rate, VOUT controlled by SVID VVCC = 4.5 V, register (65h) TOFF_FALL = 10b, Vboot = 1.1V, PROTOCOL ID = 07h, 5mV VID step 0.50 0.55 0.61 V/ms
tOFF(Fall) Soft-stop slew rate, VOUT controlled by SVID VVCC = 4.5 V, register (65h) TOFF_FALL = 11b, Vboot = 1.1V, PROTOCOL ID = 07h, 5mV VID step 0.25 0.275 0.31 V/ms
tOFF(Fall) Soft-stop slew rate, VOUT controlled by SVID VVCC = 4.5 V, register (65h) TOFF_FALL = 00b, Vboot = 1.8V, PROTOCOL ID = 04h, 10mV VID step 3.27 3.6 4.00 V/ms
tOFF(Fall) Soft-stop slew rate, VOUT controlled by SVID VVCC = 4.5 V, register (65h) TOFF_FALL = 01b, Vboot = 1.8V, PROTOCOL ID = 04h, 10mV VID step 1.64 1.8 2.00 V/ms
tOFF(Fall) Soft-stop slew rate, VOUT controlled by SVID VVCC = 4.5 V, register (65h) TOFF_FALL = 10b, Vboot = 1.8V, PROTOCOL ID = 04h, 10mV VID step 0.82 0.9 1.00 V/ms
tOFF(Fall) Soft-stop slew rate, VOUT controlled by SVID VVCC = 4.5 V, register (65h) TOFF_FALL = 11b, Vboot = 1.8V, PROTOCOL ID = 04h, 10mV VID step 0.41 0.45 0.50 V/ms
tOFF(Fall) Soft-stop slew rate, VOUT controlled by I2C VVCC = 4.5 V, register (65h) TOFF_FALL = 00b, PROTOCOL ID = 07h, 5mV VID step 2.00 2.2 2.44 V/ms
tOFF(Fall) Soft-stop slew rate, VOUT controlled by I2C VVCC = 4.5 V, register (65h) TOFF_FALL = 01b, PROTOCOL ID = 07h, 5mV VID step 1.00 1.1 1.22 V/ms
tOFF(Fall) Soft-stop slew rate, VOUT controlled by I2C VVCC = 4.5 V, register (65h) TOFF_FALL = 10b, PROTOCOL ID = 07h, 5mV VID step 0.50 0.55 0.61 V/ms
tOFF(Fall) Soft-stop slew rate, VOUT controlled by I2C VVCC = 4.5 V, register (65h) TOFF_FALL = 11b, PROTOCOL ID = 07h, 5mV VID step 0.25 0.275 0.31 V/ms
tOFF(Fall) Soft-stop slew rate, VOUT controlled by I2C VVCC = 4.5 V, register (65h) TOFF_FALL = 00b, PROTOCOL ID = 04h, 10mV VID step 3.27 3.6 4.00 V/ms
tOFF(Fall) Soft-stop slew rate, VOUT controlled by I2C VVCC = 4.5 V, register (65h) TOFF_FALL = 01b, PROTOCOL ID = 04h, 10mV VID step 1.64 1.8 2.00 V/ms
tOFF(Fall) Soft-stop slew rate, VOUT controlled by I2C VVCC = 4.5 V, register (65h) TOFF_FALL = 10b, PROTOCOL ID = 04h, 10mV VID step 0.82 0.9 1.00 V/ms
tOFF(Fall) Soft-stop slew rate, VOUT controlled by I2C VVCC = 4.5 V, register (65h) TOFF_FALL = 11b, PROTOCOL ID = 04h, 10mV VID step 0.41 0.45 0.50 V/ms
POWER STAGE
RDSON(HS) High-side MOSFET on-resistance TJ = 25°C, PVIN = 12 V, VBOOT-SW = 4.5 V 4 mΩ
RDSON(HS) High-side MOSFET on-resistance TJ = 25°C, PVIN = 12 V, VBOOT-SW = 5.0 V 3.91 mΩ
RDSON(LS) Low-side MOSFET on-resistance TJ = 25°C, PVIN = 12 V, VVCC = 4.5 V 1 mΩ
RDSON(LS) Low-side MOSFET on-resistance TJ = 25°C, PVIN = 12 V, VVCC = 5 V 0.98 mΩ
tON(min) Minimum ON pulse width VVCC = 4.5 V 50 ns
tOFF(min) Minimum OFF pulse width VVCC = 4.5 V, IO=1.5A, VOUT = VOUT(set) – 20 mV, SW falling edge to rising edge 180 ns
BOOT CIRCUIT
IBOOT(LKG) BOOT leakage current VEN = 2 V, VBOOT-SW = 5 V 150 µA
VBOOT-SW(UV_F) BOOT-SW UVLO falling threshold 2.60 2.76 V
OVERCURRENT PROTECTION
ILS(OC) Low-side valley overcurrent limit (TPS544C26) Valley current limit on LS FET, IOUT_OC_FAULT_LIMIT (46h) = 0000b 8.5 10 11.5 A
ILS(OC) Low-side valley overcurrent limit (TPS544C26) Valley current limit on LS FET, IOUT_OC_FAULT_LIMIT (46h) = 0001b 10.2 12 13.8 A
ILS(OC) Low-side valley overcurrent limit (TPS544C26) Valley current limit on LS FET, IOUT_OC_FAULT_LIMIT (46h) = 0010b 13.5 15 16.5 A
ILS(OC) Low-side valley overcurrent limit (TPS544C26) Valley current limit on LS FET, IOUT_OC_FAULT_LIMIT (46h) = 0011b 17.1 19 20.9 A
ILS(OC) Low-side valley overcurrent limit (TPS544C26) Valley current limit on LS FET, IOUT_OC_FAULT_LIMIT (46h) = 0100b 18 20 22 A
ILS(OCL) Low-side valley overcurrent limit (TPS544C26) Valley current limit on LS FET, IOUT_OC_FAULT_LIMIT (46h) = 0101b 22.5 25 27.5 A
ILS(OCL) Low-side valley overcurrent limit (TPS544C26) Valley current limit on LS FET, IOUT_OC_FAULT_LIMIT (46h) = 0110b 23.4 26 28.6 A
ILS(OCL) Low-side valley overcurrent limit (TPS544C26) Valley current limit on LS FET, IOUT_OC_FAULT_LIMIT (46h) = 0111b 27 30 33 A
ILS(OCL) Low-side valley overcurrent limit (TPS544C26) Valley current limit on LS FET, IOUT_OC_FAULT_LIMIT (46h) = 1000b 29.7 33 36.3 A
ILS(OCL) Low-side valley overcurrent limit (TPS544C26) Valley current limit on LS FET, IOUT_OC_FAULT_LIMIT (46h) = 1001b 31.5 35 38.5 A
ILS(OCL) Low-side valley overcurrent limit (TPS544C26) Valley current limit on LS FET, IOUT_OC_FAULT_LIMIT (46h) = 1010b 35.1 39 42.9 A
ILS(OCL) Low-side valley overcurrent limit (TPS544C26) Valley current limit on LS FET, IOUT_OC_FAULT_LIMIT (46h) = 1011b 36 40 44 A
ILS(OCL) Low-side valley overcurrent limit (TPS544C26) Valley current limit on LS FET, IOUT_OC_FAULT_LIMIT (46h) = 11xxb 36 40 44 A
ILS(OCW) Low-side valley overcurrent warning (TPS544C26) Valley current limit on LS FET, IOUT_OC_WARN_LIMIT (4Ah) = 000b 8.5 10 11.5 A
ILS(OCW) Low-side valley overcurrent warning (TPS544C26) Valley current limit on LS FET, IOUT_OC_WARN_LIMIT (4Ah) = 001b 13.5 15 16.5 A
ILS(OCW) Low-side valley overcurrent warning (TPS544C26) Valley current limit on LS FET, IOUT_OC_WARN_LIMIT (4Ah) = 010b 18 20 22 A
ILS(OCW) Low-side valley overcurrent warning (TPS544C26) Valley current limit on LS FET, IOUT_OC_WARN_LIMIT (4Ah) = 011b 22.5 25 27.5 A
ILS(OCW) Low-side valley overcurrent warning (TPS544C26) Valley current limit on LS FET, IOUT_OC_WARN_LIMIT (4Ah) = 100b 27 30 33 A
ILS(OCW) Low-side valley overcurrent warning (TPS544C26) Valley current limit on LS FET, IOUT_OC_WARN_LIMIT (4Ah) = 101b 31.5 35 38.5 A
ILS(OCW) Low-side valley overcurrent warning (TPS544C26) Valley current limit on LS FET, IOUT_OC_WARN_LIMIT (4Ah) = 11xb 36 40 44 A
ILS(NOC) Low-side negative overcurrent limit Sinking current limit on LS FET, IOUT_NOC_LIMIT (B4h) = 00b, ICCMAX ≥ 15A –18 –20 –22 A
ILS(NOC) Low-side negative overcurrent limit Sinking current limit on LS FET, IOUT_NOC_LIMIT (B4h) = 00b, ICCMAX ≤ 10 A –8.5 –10 –11.5 A
ILS(NOC) Low-side negative overcurrent limit Sinking current limit on LS FET, IOUT_NOC_LIMIT (B4h) = 01b, ICCMAX ≥ 15A –13.5 –15 –16.5 A
ILS(NOC) Low-side negative overcurrent limit Sinking current limit on LS FET, IOUT_NOC_LIMIT (B4h) = 01b, ICCMAX ≤ 10 A –6.37 –7.5 –8.63 A
ILS(NOC) Low-side negative overcurrent limit Sinking current limit on LS FET, IOUT_NOC_LIMIT (B4h) = 10b, ICCMAX ≥ 15A –10.2 –12 –13.8 A
ILS(NOC) Low-side negative overcurrent limit Sinking current limit on LS FET, IOUT_NOC_LIMIT (B4h) = 10b, ICCMAX ≤ 10 A –5.1 –6 –6.9 A
ILS(NOC) Low-side negative overcurrent limit Sinking current limit on LS FET, IOUT_NOC_LIMIT (B4h) = 11b, ICCMAX ≥ 15A –8.5 –10 –11.5 A
ILS(NOC) Low-side negative overcurrent limit Sinking current limit on LS FET, IOUT_NOC_LIMIT (B4h) = 11b, ICCMAX ≤ 10 A –4.25 –5 –5.75 A
IZC Zero-cross detection current threshold VIN = 12 V, VVCC = 4.5 V, SEL_ZC = 00b, enter DCM 1200 mA
IZC Zero-cross detection current threshold VIN = 12 V, VVCC = 4.5 V, SEL_ZC = 00b, exit DCM 1500 mA
IZC Zero-cross detection current threshold VIN = 12 V, VVCC = 4.5 V, SEL_ZC = 01b, enter DCM 900 mA
IZC Zero-cross detection current threshold VIN = 12 V, VVCC = 4.5 V, SEL_ZC = 01b, exit DCM 1200 mA
IZC Zero-cross detection current threshold VIN = 12 V, VVCC = 4.5 V, SEL_ZC = 10b, enter DCM 0 mA
IZC Zero-cross detection current threshold VIN = 12 V, VVCC = 4.5 V, SEL_ZC = 10b, exit DCM 300 mA
IZC Zero-cross detection current threshold VIN = 12 V, VVCC = 4.5 V, SEL_ZC = 11b, enter DCM –300 mA
IZC Zero-cross detection current threshold VIN = 12 V, VVCC = 4.5 V, SEL_ZC = 11b, exit DCM 0 mA
Response delay before entering Hiccup UV RESPONSE_DELAY = 00b 2 µs
Response delay before entering Hiccup UV RESPONSE_DELAY = 01b 16 µs
Response delay before entering Hiccup UV RESPONSE_DELAY = 10b 64 µs
Response delay before entering Hiccup UV RESPONSE_DELAY = 11b 256 µs
Hiccup sleep time before a restart 56 ms
OUTPUT OVP AND UVP
VOVP Vout tracking overvoltage protection (OVP) threshold, offset above Vout (VOSNS –  GOSNS) rising. (40h) VOUT_OV_FAULT_LIMIT = 00b 80 100 120 mV
VOVP Vout tracking overvoltage protection (OVP) threshold, offset above Vout (VOSNS –  GOSNS) rising. (40h) VOUT_OV_FAULT_LIMIT = 01b 120 150 180 mV
VOVP Vout tracking overvoltage protection (OVP) threshold, offset above Vout (VOSNS –  GOSNS) rising. (40h) VOUT_OV_FAULT_LIMIT = 10b 160 200 240 mV
VOVP Vout tracking overvoltage protection (OVP) threshold, offset above Vout (VOSNS –  GOSNS) rising. (40h) VOUT_OV_FAULT_LIMIT = 11b 240 300 360 mV
Vout tracking OVP de-glitch time 2 µs
VFixOV Vout fixed OVP threshold, 5mV step (VOSNS –  GOSNS) rising. (CFh) FAULT_CTRL2, SEL_FIX_OVF = 0b, and (CCh) PROTOCOL_ID_SVID, PROTOCOL_ID<7:6> = 01b or 10b (5mV step) 1.425 1.5 1.575 V
VFixOV Vout fixed OVP threshold, 5mV step (VOSNS –  GOSNS) rising. (CFh) FAULT_CTRL2, SEL_FIX_OVF = 1b, and (CCh) PROTOCOL_ID_SVID, PROTOCOL_ID<7:6> = 01b or 10b (5mV step) 1.71 1.8 1.89 V
VFixOV Vout fixed OVP threshold, 10mV step (VOSNS –  GOSNS) rising. (CFh) FAULT_CTRL2, SEL_FIX_OVF = 0b, and (CCh) PROTOCOL_ID_SVID, PROTOCOL_ID<7:6> = 00b or 11b (10mV step) 2.33 2.4 2.47 V
VFixOV Vout fixed OVP threshold, 10mV step (VOSNS –  GOSNS) rising. (CFh) FAULT_CTRL2, SEL_FIX_OVF = 1b, and (CCh) PROTOCOL_ID_SVID, PROTOCOL_ID<7:6> = 00b or 11b (10mV step) 2.93 3.0 3.07 V
Vout fixed OVP de-glitch time 2 µs
VUVP Vout tracking undervoltage protection (UVP) threshold, offset below Vout (VOSNS –  GOSNS) falling. (44h) VOUT_UV_FAULT_LIMIT = 00b –120 –150 –180 mV
VUVP Vout tracking undervoltage protection (UVP) threshold, offset below Vout (VOSNS –  GOSNS) falling. (44h) VOUT_UV_FAULT_LIMIT = 01b –160 –200 –240 mV
VUVP Vout tracking undervoltage protection (UVP) threshold, offset below Vout (VOSNS –  GOSNS) falling. (44h) VOUT_UV_FAULT_LIMIT = 10b –160 –200 –240 mV
VUVP Vout tracking undervoltage protection (UVP) threshold, offset below Vout (VOSNS –  GOSNS) falling. (44h) VOUT_UV_FAULT_LIMIT = 11b –240 –300 –360 mV
Vout tracking UVP response delay time (45h) VOUT_UV_FAULT_RESPONSE, RESPONSE_DELAY<1:0> = 00b. From UV detection to tri-state of the power FETs 2 4 µs
Vout tracking UVP response delay time (45h) VOUT_UV_FAULT_RESPONSE, RESPONSE_DELAY<1:0> = 01b. From UV detection to tri-state of the power FETs 14.4 16 17.6 µs
Vout tracking UVP response delay time (45h) VOUT_UV_FAULT_RESPONSE, RESPONSE_DELAY<1:0> = 10b. From UV detection to tri-state of the power FETs 57.6 64 70.4 µs
Vout tracking UVP response delay time (45h) VOUT_UV_FAULT_RESPONSE, RESPONSE_DELAY<1:0> = 11b. From UV detection to tri-state of the power FETs 230.4 256 281.6 µs
VR READY AND CATASTROPHIC FAULT
VOL(VRRDY) VRRDY pin output low-level voltage IVRRDY = 10 mA, VIN = 12 V, VVCC = 4.5 V 300 mV
ILKG(VRRDY) VRRDY pin Leakage current when open drain output is high Rpullup = 10 kΩ, VVRRDY = 5 V 5 µA
Min VCC for valid VRRDY pin output PVIN = 0 V, VEN = 0 V, Rpullup = 10 kΩ, VVRRDY ≤ 0.3 V 1.2 V
CAT_FAULT# pin output low-level voltage Rpullup = 4.99 kΩ, Vpullup = 3.3 V 210 300 mV
CAT_FAULT# pin Leakage current when open drain output is high Rpullup = 4.99 kΩ, Vpullup = 3.3 V 5 µA
OUTPUT DISCHARGE
Output discharge on VOSNS pin VIN = 12 V, VVCC = Internal LDO, VVOSNS = 0.5 V, EN=0V 40 Ω
THERMAL SHUTDOWN
TJ(SD) Thermal shutdown threshold (1) Junction temperature rising 153 166 °C
TJ(HYS) Thermal shutdown hysteresis (1) 30 °C
MEASUREMENT SYSTEM (I2C)
MIOUT(rng) Output current measurement range (C0h) ICC_MAX = 40 A 0 40 A
MIOUT(acc) Output current measurement accuracy (C0h) ICC_MAX = 40 A, 0 ≤ IOUT ≤ 4 A, –40°C ≤ TJ ≤ 125°C –0.625 0.625 A
MIOUT(acc) Output current measurement accuracy (C0h) ICC_MAX = 40 A, IOUT = 12 A, –40°C ≤ TJ ≤ 125°C –8% 8%
MIOUT(acc) Output current measurement accuracy (C0h) ICC_MAX = 40 A, 24 A ≤ IOUT < 40 A, –40°C ≤ TJ ≤ 125°C –6% 6%
MIOUT(lsb) Output current measurement bit resolution (C0h) ICC_MAX = 40 A 0.1563 A
MVOUT(rng) Output voltage measurement range 0 3.04 V
MVOUT(acc) Output voltage measurement accuracy 0.75 V ≤ VOUT ≤ 1.5 V, PROTOCOL ID =  07h, 5mV VID step –19 19 mV
MVOUT(acc) Output voltage measurement accuracy 1.5 V < VOUT ≤ 3.0 V, PROTOCOL ID =  04h, 10mV VID step –37.5 37.5 mV
MVOUT(lsb) Output voltage measurement bit resolution PROTOCOL ID =  07h, 5mV VID step 6.25 mV
MVOUT(lsb) Output voltage measurement bit resolution PROTOCOL ID =  04h, 10mV VID step 12.5 mV
MPIN(rng) Input power measurement range (6Bh) PIN_OP_WARN_LIMIT = 000b (360 W) 0 360 W
MPIN(acc) Input power measurement accuracy datapoint Room Temp, 12V, 15A, 180W 180 W
MPIN(acc) Input power measurement accuracy datapoint Room Temp, 12V, 25A, 300W 300 W
MPIN(acc) Input power measurement accuracy % %
MPIN(lsb) Input power measurement bit resolution W
MVIN(rng) Input voltage measurement range VINSNSM – AGND 8 16 V
MVIN(acc) Input voltage measurement accuracy datapoint VINSNSM – AGND. TJ = 0℃ to 85℃ 8 V
MVIN(acc) Input voltage measurement accuracy datapoint VINSNSM – AGND. TJ = 0℃ to 85℃ 12 V
MVIN(acc) Input voltage measurement accuracy datapoint VINSNSM – AGND. TJ = 0℃ to 85℃ 16 V
MVIN(acc) Input voltage measurement accuracy 8 V≤ VINSNSM ≤ 16 V % %
MVIN(lsb) Input voltage measurement bit resolution VINSNSM – AGND V
MIIN(rng) Input current measurement range (B3h) PIN_SENSE_RES = 100b (1.0 mΩ), 101b (0.5 mΩ) 0 32 A
MIIN(acc) Input current measurement accuracy datapoint Room temp, PIN_SENSE_RES set accordingly 15 A
MIIN(acc) Input current measurement accuracy datapoint Room temp, PIN_SENSE_RES set accordingly 25 A
MIIN(acc) Input current measurement accuracy % %
MIIN(lsb) Input current measurement bit resolution A
MTSNS(rng) Internal temperature sense range –40 125 °C
MTSNS(acc) Internal temperature sense accuracy datapoint -40 °C
MTSNS(acc) Internal temperature sense accuracy datapoint 0 °C
MTSNS(acc) Internal temperature sense accuracy datapoint 25 °C
MTSNS(acc) Internal temperature sense accuracy datapoint 85 °C
MTSNS(acc) Internal temperature sense accuracy datapoint 125 °C
MTSNS(acc) Internal temperature sense accuracy –40°C ≤ TJ ≤ 125°C % %
MTSNS(lsb) Internal temperature sense bit resolution °C
SVID Timing and Physical Characteristics
CPAD_SVID SVID pin pad capacitance(1) 0 4 pF
CPIN_SVID SVID pin capacitance(1) 0 5 pF
VMAX_SVID VDS max open drain buffer to accommodate ringing on bus –1 3.3 V
VIL_SVID SV_CLK, SV_DIO input low voltage 0.45 0.5 0.55 V
VIH_SVID SV_CLK, SV_DIO input high voltage 0.54 0.59 0.64 V
VHYS_SVID SV_CLK, SV_DIO input voltage hysteresis 0.05 V
RRSVIDL Open Drain Pulldown resistance SV_DIO, SV_ALERT# pins pulldown resistance 4 8 13 Ω
ILKG_SVID Input leakage current Pullup source = 5.5 V, off state 20 µA
DCLK_SVID SVID clock duty ratios (Period and duty cycle are measured with respect to 0.5 x VccIO) 0.4 0.6
tCO_VR_SVID VR Clock to Data delay without board parasitic 12 ns
tSU_VR_SVID Setup time of data at VR side 7 ns
tH_VR_SVID Hold time of data at VR side 14 ns
tCO_CPU_SVID CPU Clock to Data delay  Measured at bump –3.6 0.65 ns
tSU_CPU_SVID Setup time of data at CPU side 1 ns
tH_CPU_SVID Hold time of data at CPU side 3 ns
SRF_DATA Falling slew rate of SV_DIO(1) SV_DIO from 0.735V to 0.315V, Rpu=64.9Ω 1.2 4 V/ns
SRR_DATA Rising slew rate of SV_DIO(1) SV_DIO from 0.315V to 0.735V, Rpu=64.9Ω 1.1 3.6 V/ns
SRF_ALERT Falling slew rate of SV_ALERT#(1) SV_ALERT# from 0.735V to 0.315V, Rpu=75Ω 1.25 4.2 V/ns
SRR_ALERT Rising slew rate of SV_ALERT#(1) SV_ALERT# from 0.315V to 0.735V, Rpu=75Ω 1.15 3.3 V/ns
FREQSVID Max SVID Clock frequency Support 43 MHz
I2C Timing and Physical Characteristics
FREQI2C I2C operating frequency range 50 1000 kHz
VIH_I2C SM_CLK, SM_DIO High-level input voltage 0.535 0.585 0.635 V
VIL_I2C SM_CLK, SM_DIO Low-level input voltage 0.465 0.515 0.565 V
VHYS_I2C SM_CLK, SM_DIO Input voltage hysteresis 0.05 V
NWRNVM Number of NVM writeable cycles (1) –40°C ≤ TJ ≤ 125°C 1000 Cycles
CBUS_I2C I2C bus capacitance on each bus line(1) 0 400 pF
CPIN_I2C I2C pin capacitance(1) 0 10 pF
tH_STA Hold time for a (repeated) START condition 0.26 µs
tLOW Low period of SM_CLK 0.5 µs
tHIGH High period of SM_CLK 0.26 µs
tSU_STA Setup time for a repeated START condition 0.26 µs
tH_I2C I2C DATA hold time 0 µs
tSU_I2C I2C DATA setup time 50 ns
tR_I2C SM_CLK and SM_DIO rise time(1) 100 kHz class 1000 ns
400 kHz class 300 ns
1000 kHz class 120 ns
tF_I2C SM_CLK and SM_DIO fall time(1) 100 kHz class 1000 ns
400 kHz class 300 ns
1000 kHz class 120 ns
tSU_STO Setup time for a STOP condition 0.26 µs
tBUF Bus free time between a STOP and START condition 0.5 µs
(1) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purpose of TI's product warranty.