ZHCSR16 September   2022 TPS544C26

ADVANCE INFORMATION  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Internal VCC LDO and Using an External Bias on VCC/VDRV Pin
      2. 7.3.2  Input Undervoltage Lockout (UVLO)
        1. 7.3.2.1 Fixed VCC UVLO
        2. 7.3.2.2 Fixed VDRV UVLO
        3. 7.3.2.3 Programmable PVIN UVLO
        4. 7.3.2.4 Enable
      3. 7.3.3  Differential Remote Sense and Internal Feedback Divider
      4. 7.3.4  Set the Output Voltage and VID Table
      5. 7.3.5  Startup and Shutdown
      6. 7.3.6  Dynamic Voltage Slew Rate
      7. 7.3.7  Adaptive Voltage Positioning (Droop) and DC Load Line (DCLL)
      8. 7.3.8  Loop Compensation
      9. 7.3.9  Set Switching Frequency
      10. 7.3.10 Switching Node (SW)
      11. 7.3.11 Overcurrent Limit and Low-side Current Sense
      12. 7.3.12 Negative Overcurrent Limit
      13. 7.3.13 Zero-Crossing Detection
      14. 7.3.14 Input Overvoltage Protection
      15. 7.3.15 Output Overvoltage and Undervoltage Protection
      16. 7.3.16 Overtemperature Protection
      17. 7.3.17 VR Ready
      18. 7.3.18 Catastrophic Fault Alert: CAT_FAULT#
      19. 7.3.19 Telemetry
      20. 7.3.20 I2C Interface General Description
        1. 7.3.20.1 Setting the I2C Address
        2. 7.3.20.2 I2C Write Protection
        3. 7.3.20.3 I2C Registers With Special Handling
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forced Continuous-Conduction Mode
      2. 7.4.2 Auto-Skip Eco-mode™ Light Load Operation
    5. 7.5 Programming
      1. 7.5.1 Supported I2C Registers
      2. 7.5.2 Support of Intel SVID Interface
    6. 7.6 Register Maps
      1. 7.6.1  (01h) OPERATION
      2. 7.6.2  (02h) ON_OFF_CONFIG
      3. 7.6.3  (03h) CLEAR_FAULTS
      4. 7.6.4  (15h) STORE_USER_ALL
      5. 7.6.5  (16h) RESTORE_USER_ALL
      6. 7.6.6  (33h) FREQUENCY_SWITCH
      7. 7.6.7  (35h) VIN_ON
      8. 7.6.8  (36h) VIN_OFF
      9. 7.6.9  (40h) VOUT_OV_FAULT_LIMIT
      10. 7.6.10 (41h) VOUT_OV_FAULT_RESPONSE
      11. 7.6.11 (42h) VOUT_OV_WARN_LIMIT
      12. 7.6.12 (43h) VOUT_UV_WARN_LIMIT
      13. 7.6.13 (44h) VOUT_UV_FAULT_LIMIT
      14. 7.6.14 (45h) VOUT_UV_FAULT_RESPONSE
      15. 7.6.15 (46h) IOUT_OC_FAULT_LIMIT
      16. 7.6.16 (4Fh) OT_FAULT_LIMIT
      17. 7.6.17 (50h) OT_FAULT_RESPONSE
      18. 7.6.18 (51h) OT_WARN_LIMIT
      19. 7.6.19 (55h) VIN_OV_FAULT_LIMIT
      20. 7.6.20 (60h) TON_DELAY
      21. 7.6.21 (61h) TON_RISE
      22. 7.6.22 (64h) TOFF_DELAY
      23. 7.6.23 (65h) TOFF_FALL
      24. 7.6.24 (6Bh) PIN_OP_WARN_LIMIT
      25. 7.6.25 (7Ah) STATUS_VOUT
      26. 7.6.26 (7Bh) STATUS_IOUT
      27. 7.6.27 (7Ch) STATUS_INPUT
      28. 7.6.28 (7Dh) STATUS_TEMPERATURE
      29. 7.6.29 (80h) STATUS_MFR_SPECIFIC
      30. 7.6.30 (88h) READ_VIN
      31. 7.6.31 (89h) READ_IIN
      32. 7.6.32 (8Bh) READ_VOUT
      33. 7.6.33 (8Ch) READ_IOUT
      34. 7.6.34 (8Dh) READ_TEMPERATURE_1
      35. 7.6.35 (97h) READ_PIN
      36. 7.6.36 (A0h) SYS_CFG_USER1
      37. 7.6.37 (A2h) I2C_ADDR
      38. 7.6.38 (A3h) SVID_ADDR
      39. 7.6.39 (A4h) IMON_CAL
      40. 7.6.40 (A5h) IIN_CAL
      41. 7.6.41 (A6h) VOUT_CMD
      42. 7.6.42 (A7h) VID_SETTING
      43. 7.6.43 (A8h) I2C_OFFSET
      44. 7.6.44 (A9h) COMP1_MAIN
      45. 7.6.45 (AAh) COMP2_MAIN
      46. 7.6.46 (ABh) COMP1_ALT
      47. 7.6.47 (ACh) COMP2_ALT
      48. 7.6.48 (ADh) COMP3
      49. 7.6.49 (AFh) DVS_CFG
      50. 7.6.50 (B0h) DVID_OFFSET
      51. 7.6.51 (B1h) REG_LOCK
      52. 7.6.52 (B3h) PIN_SENSE_RES
      53. 7.6.53 (B4h) IOUT_NOC_LIMIT
      54. 7.6.54 (B5h) USER_DATA_01
      55. 7.6.55 (B6h) USER_DATA_02
      56. 7.6.56 (BAh) STATUS1_SVID
      57. 7.6.57 (BBh) STATUS2_SVID
      58. 7.6.58 (BCh) CAPABILITY
      59. 7.6.59 (BDh) EXT_CAPABILITY_VIDOMAX_H
      60. 7.6.60 (BEh) VIDOMAX_L
      61. 7.6.61 (C0h) ICC_MAX
      62. 7.6.62 (C1h) TEMP_MAX
      63. 7.6.63 (C2h) PROTOCOL_ID_SVID
      64. 7.6.64 (C6h) VENDOR_ID
      65. 7.6.65 (C8h) PRODUCT_ID
      66. 7.6.66 (C9h) PRODUCT_REV_ID
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Inductor Selection
        2. 8.2.3.2 Input Capacitor Selection
        3. 8.2.3.3 Output Capacitor Selection
        4. 8.2.3.4 VCC/VRDV Bypass Capacitor
        5. 8.2.3.5 BOOT Capacitor Selection
        6. 8.2.3.6 RSENSE Selection
        7. 8.2.3.7 VINSENP and VINSENN Capacitor Selection
        8. 8.2.3.8 VRRDY Pullup Resistor Selection
        9. 8.2.3.9 I2C Address Resistor Selection
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Performance on TPS544C26EVM
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 术语表
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information

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7.3.5 Startup and Shutdown

Startup

The startup sequence includes three sequential periods. During the first period, the device does initialization which includes building up internal LDOs and references, register value initialization, pin strap detection, enabling digital interface, and so forth. The initialization, which is not gated by EN pin voltage, starts as long as VCC/VDRV pin voltage is above the VCC UVLO rising threshold (3.2-V typical). The length of this period is about 200 μs for TPS544C26 device. The I2C communication including both read and write operations is allowed after finishing the initialization.

Once the EN pin voltage crosses above EN high threshold (typically 1.2 V) the device moves to the second period, power-on delay. The power-on delay is programmable in TPS544C26 through register Section 7.6.20 with minimum 0.5 ms delay and maximum 2 ms delay.

The VOUT soft-start is the third period. A soft-start ramp, which is an internal signal, starts when the chosen power-on delay finishes. The soft-start time can be selected in register Section 7.6.21 with options of 1 ms, 2 ms, 4 ms, 8 ms, and 16 ms. When starting up without pre-bias on the output, the VOUT ramps up from 0 V to either the selected Vboot value or the programmabled VOUT_CMD value (depending on the VOUT_CTRL setting) to avoid the inrush current by the output capacitor charging, and also minimize VOUT overshoot. The VOUT ramping up slew rate is determined by VOUT step (set by PROTOCOL_ID in register (C2h) PROTOCOL_ID_SVID, Vboot and TON_RISE values, and the actual soft-start time can vary from the selected TON_RISE value. Table 7-7 shows more details.

For the startup with a pre-biased output the device limits current from being discharged from the prebiased output voltage by preventing the low-side FET from forcing the SW node low until after the first PWM pulse turns on the high-side FET. Once the increasing reference voltage exceeds the feedback voltage which is internally divided down from (VOSNS−GOSNS) level, the high-side SW pulses start. This enables a smooth startup with a pre-biased output.

Once VOUT reaches the regulation value and VRRDY delay expires, the converter asserts VRRDY pin and becomes ready for SVID commands. The VRRDY delay can be programmed in (A0h) SYS_CFG_USER1 register and the default value is set to 0 ms to meet SVID communication requirement.

Table 7-7 Soft-start Slew Rate and the Actual Soft-start Time
VOUT_CTRLVOUT Control MethodVOUT StepSoft-start Slew Rate (V/ms)Actual Soft-start Time (ms)
00bSVID only5 mV or 10 mVVboot / TON_RISETON_RISE
01bSVID + I2C5 mV or 10 mVVboot / TON_RISE(1 + I2C_OFFSET / Vboot) × TON_RISE
10b or 11bI2C only5 mV1.1 V / TON_RISE(VOUT_CMD + I2C_OFFSET) / 1.1 V × TON_RISE
10b or 11bI2C only10 mV1.8 V / TON_RISE(VOUT_CMD + I2C_OFFSET) / 1.1 V × TON_RISE

Shutdown

The TPS544C26 device also offers programmable soft-stop feature through I2C register (65h) TOFF_FALL with 0.5 ms, 1 ms, 2 ms, and 4 ms options. The soft-stop feature force a controlled decrease of the output voltage from regulation to 200 mV. Once Vout is discharged to 200 mV level the power stage stops switching and goes to tri-state. There can be negative inductor current forced during the TOFF_FALL time to discharge the output voltage. This feature can be enabled or disabled through I2C. Configuring EN_SOFT_STOP bit in register Section 7.6.36 to value “0” disables the soft-stop feature and automatically sets TOFF_DELAY to 0 ms.

In the case of Soft-stop is enabled, after a stop condition is received and the selected TOFF_DELAY delay expires, the TPS544C26 device enters the soft-stop operation during which the control loop actively controls the discharge slew rate of the output voltage. The power stage continues switching while the internal reference ramps down linearly. The discharge slew rate during this phase is determined by the selected boot up voltage (not the current output voltage) and the selected TOFF_FALL time. Once Vout is discharged to 200 mV level the power stage stops switching and goes to tri-state. The Vout discharge continues but the discharge slew rate is controlled by the load current. With this discharge operation, the TPS544C26 device controls the soft-stop slew rate rather the total soft-stop time, thus the total VOUT discharge time (a.k.a soft-stop time) can vary from the register (65h) TOFF_FALL value. Another word, The TOFF_FALL time is utilized to set the internal reference DAC ramp-down time from the regulation level to 0 mV. For example, under heavy load condition, the total soft-stop time from VOUT regulation level to zero volt is likely shorter than the programmed TOFF_FALL value. Under light load, the total soft-stop time likely becomes longer than the programmed TOFF_FALL value. Table Table 7-8 shows more details.

In the case of soft-stop feature is disabled through the EN_SOFT_STOP bit in (A0h) SYS_CFG_USER1 register, both high-side and low-side FET drivers are turned off immediately at the time when a stop condition is received (as programmed by the (02h) ON_OFF_CONFIG command), and the output voltage discharge slew rate is controlled by the external load.

Table 7-8 Soft-stop Slew Rate and the Actual Soft-stop Time
VOUT_CTRLVOUT Control MethodVOUT StepSoft-stop Slew Rate (V/ms)Actual Soft-stop Time (ms)
00bSVID only5 mV or 10 mVVboot / TOFF_FALL(Current VOUT − 0.2 V) / Vboot × TOFF_FALL + tDELAY(1)
01bSVID + I2C5 mV or 10 mVVboot / TOFF_FALL(Current VOUT − 0.2 V) / Vboot × TOFF_FALL + tDELAY(1)
10b or 11bI2C only5 mV1.1 V / TOFF_FALL(Current VOUT − 0.2 V) / 1.1 V × TOFF_FALL + tDELAY(1)
10b or 11bI2C only10 mV1.8 V / TOFF_FALL(Current VOUT − 0.2 V) / 1.8 V × TOFF_FALL + tDELAY(1)
(1) Power stage switching ends at VOUT = 200 mV. tDELAY is determined by output capacitance and the load current.