ZHCSR16 September   2022 TPS544C26

ADVANCE INFORMATION  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Internal VCC LDO and Using an External Bias on VCC/VDRV Pin
      2. 7.3.2  Input Undervoltage Lockout (UVLO)
        1. 7.3.2.1 Fixed VCC UVLO
        2. 7.3.2.2 Fixed VDRV UVLO
        3. 7.3.2.3 Programmable PVIN UVLO
        4. 7.3.2.4 Enable
      3. 7.3.3  Differential Remote Sense and Internal Feedback Divider
      4. 7.3.4  Set the Output Voltage and VID Table
      5. 7.3.5  Startup and Shutdown
      6. 7.3.6  Dynamic Voltage Slew Rate
      7. 7.3.7  Adaptive Voltage Positioning (Droop) and DC Load Line (DCLL)
      8. 7.3.8  Loop Compensation
      9. 7.3.9  Set Switching Frequency
      10. 7.3.10 Switching Node (SW)
      11. 7.3.11 Overcurrent Limit and Low-side Current Sense
      12. 7.3.12 Negative Overcurrent Limit
      13. 7.3.13 Zero-Crossing Detection
      14. 7.3.14 Input Overvoltage Protection
      15. 7.3.15 Output Overvoltage and Undervoltage Protection
      16. 7.3.16 Overtemperature Protection
      17. 7.3.17 VR Ready
      18. 7.3.18 Catastrophic Fault Alert: CAT_FAULT#
      19. 7.3.19 Telemetry
      20. 7.3.20 I2C Interface General Description
        1. 7.3.20.1 Setting the I2C Address
        2. 7.3.20.2 I2C Write Protection
        3. 7.3.20.3 I2C Registers With Special Handling
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forced Continuous-Conduction Mode
      2. 7.4.2 Auto-Skip Eco-mode™ Light Load Operation
    5. 7.5 Programming
      1. 7.5.1 Supported I2C Registers
      2. 7.5.2 Support of Intel SVID Interface
    6. 7.6 Register Maps
      1. 7.6.1  (01h) OPERATION
      2. 7.6.2  (02h) ON_OFF_CONFIG
      3. 7.6.3  (03h) CLEAR_FAULTS
      4. 7.6.4  (15h) STORE_USER_ALL
      5. 7.6.5  (16h) RESTORE_USER_ALL
      6. 7.6.6  (33h) FREQUENCY_SWITCH
      7. 7.6.7  (35h) VIN_ON
      8. 7.6.8  (36h) VIN_OFF
      9. 7.6.9  (40h) VOUT_OV_FAULT_LIMIT
      10. 7.6.10 (41h) VOUT_OV_FAULT_RESPONSE
      11. 7.6.11 (42h) VOUT_OV_WARN_LIMIT
      12. 7.6.12 (43h) VOUT_UV_WARN_LIMIT
      13. 7.6.13 (44h) VOUT_UV_FAULT_LIMIT
      14. 7.6.14 (45h) VOUT_UV_FAULT_RESPONSE
      15. 7.6.15 (46h) IOUT_OC_FAULT_LIMIT
      16. 7.6.16 (4Fh) OT_FAULT_LIMIT
      17. 7.6.17 (50h) OT_FAULT_RESPONSE
      18. 7.6.18 (51h) OT_WARN_LIMIT
      19. 7.6.19 (55h) VIN_OV_FAULT_LIMIT
      20. 7.6.20 (60h) TON_DELAY
      21. 7.6.21 (61h) TON_RISE
      22. 7.6.22 (64h) TOFF_DELAY
      23. 7.6.23 (65h) TOFF_FALL
      24. 7.6.24 (6Bh) PIN_OP_WARN_LIMIT
      25. 7.6.25 (7Ah) STATUS_VOUT
      26. 7.6.26 (7Bh) STATUS_IOUT
      27. 7.6.27 (7Ch) STATUS_INPUT
      28. 7.6.28 (7Dh) STATUS_TEMPERATURE
      29. 7.6.29 (80h) STATUS_MFR_SPECIFIC
      30. 7.6.30 (88h) READ_VIN
      31. 7.6.31 (89h) READ_IIN
      32. 7.6.32 (8Bh) READ_VOUT
      33. 7.6.33 (8Ch) READ_IOUT
      34. 7.6.34 (8Dh) READ_TEMPERATURE_1
      35. 7.6.35 (97h) READ_PIN
      36. 7.6.36 (A0h) SYS_CFG_USER1
      37. 7.6.37 (A2h) I2C_ADDR
      38. 7.6.38 (A3h) SVID_ADDR
      39. 7.6.39 (A4h) IMON_CAL
      40. 7.6.40 (A5h) IIN_CAL
      41. 7.6.41 (A6h) VOUT_CMD
      42. 7.6.42 (A7h) VID_SETTING
      43. 7.6.43 (A8h) I2C_OFFSET
      44. 7.6.44 (A9h) COMP1_MAIN
      45. 7.6.45 (AAh) COMP2_MAIN
      46. 7.6.46 (ABh) COMP1_ALT
      47. 7.6.47 (ACh) COMP2_ALT
      48. 7.6.48 (ADh) COMP3
      49. 7.6.49 (AFh) DVS_CFG
      50. 7.6.50 (B0h) DVID_OFFSET
      51. 7.6.51 (B1h) REG_LOCK
      52. 7.6.52 (B3h) PIN_SENSE_RES
      53. 7.6.53 (B4h) IOUT_NOC_LIMIT
      54. 7.6.54 (B5h) USER_DATA_01
      55. 7.6.55 (B6h) USER_DATA_02
      56. 7.6.56 (BAh) STATUS1_SVID
      57. 7.6.57 (BBh) STATUS2_SVID
      58. 7.6.58 (BCh) CAPABILITY
      59. 7.6.59 (BDh) EXT_CAPABILITY_VIDOMAX_H
      60. 7.6.60 (BEh) VIDOMAX_L
      61. 7.6.61 (C0h) ICC_MAX
      62. 7.6.62 (C1h) TEMP_MAX
      63. 7.6.63 (C2h) PROTOCOL_ID_SVID
      64. 7.6.64 (C6h) VENDOR_ID
      65. 7.6.65 (C8h) PRODUCT_ID
      66. 7.6.66 (C9h) PRODUCT_REV_ID
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Inductor Selection
        2. 8.2.3.2 Input Capacitor Selection
        3. 8.2.3.3 Output Capacitor Selection
        4. 8.2.3.4 VCC/VRDV Bypass Capacitor
        5. 8.2.3.5 BOOT Capacitor Selection
        6. 8.2.3.6 RSENSE Selection
        7. 8.2.3.7 VINSENP and VINSENN Capacitor Selection
        8. 8.2.3.8 VRRDY Pullup Resistor Selection
        9. 8.2.3.9 I2C Address Resistor Selection
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Performance on TPS544C26EVM
  9. Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 术语表
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

(ADh) COMP3

CMD AddressADh
Write Transaction:Write Byte
Read Transaction:Read Byte
Format: Unsigned Binary (1 byte)
NVM Backup:EEPROM
Updates:On-the-fly

The COMP3 command contains 4 fields for configuring the control loop.

The EN_SS_DCM bit sets the operation mode during the soft-start ramp. With value "1" on this bit, the device is forced to under DCM operation during the soft-start ramp. This bit doesn't control the operation mode after the soft-start ramp completes.

The SEL_NOC_TON bit selects the on-time reference for a NOC operation and thus determines the high-side FET conduction time during a NOC operation period. The on-time option selected here can help to avoid two undesired behaviors:

  • For relatively low VOUT applications (such as VOUT = 1.1 V) using longer tON_NOC helps to prevent negative current run-away behavior. A NOC run-away behavior occurs when the inductor current moves more negatively during low-side FET conduction time than the movement during high-side conduction time. A NOC run-away behavior can lead to excessive stress on low-side FET and raise the concern of FET reliability.
  • For applications with an extra large inductor current ripple (≥ 10 A) and the NOC threshold is set to a less negative value (for example NOC threshold = −7.5 A), the average current during the NOC operation is likely not that negative. This leads to insufficient discharge on VOUT and thus the load is stressed under the overvoltage condition for a longer period. To build sufficient negative current during the NOC operation, select the shorter tON_NOC to reduce the positive inductor current movement during the high-side on-time. A design example of this kind of case is VCCFA_EHV rail which can have the following configuration: PVIN = 12 V, VOUT = 1.8 V, fSW = 1 MHz, LOUT = 150 nH, ICC_MAX = 10 A, and NOC threshold = −7.5 A. To have sufficient discharge on VOUT, the design can either select the shorter tON_NOC or set ICC_MAX to 15 A so that the NOC threshold is more negative (such as −15 A).

These SEL_LO_CS bits select the LOUT (output inductor value) for the current sensing circuit. The TPS544C26 IC utilizes the output inductor value entered here to build an accurate output from the current sense circuit. Please choose a value closest to the inductor that is used in a BOM. For any inductor value higher than 400 nH, set SEL_LO_CS to 11b. Selecting a value that is significantly different from the real inductor (for example, 400 nH used but 100 nH selected) can lead to an inaccurate current sense output which can cause unexpected control loop behavior and also an inaccurate READ_IOUT telemetry report.

The DCLL bits determine the DC load line setting. Select a DCLL value per the requirement from the processor or the load, otherwise, the load regulation can be out of expectation.

Return to Supported I2C and Default Values.

Figure 7-49 (ADh) COMP3 Register Map
76543210
RR/WR/WR/WR/WR/WR/WR/W
Reserved EN_SS_DCM SEL_NOC_TON SEL_LO_CS DCLL
LEGEND: R/W = Read/Write; R = Read only
Table 7-65 Register Field Descriptions
BitFieldAccessResetDescription
7 ReservedR0bNot used and always set to 0.
6 EN_SS_DCM R/W NVM

0b: the operation during the soft-start ramp follows the configuration set by the FCCM bit in (A0h) SYS_CFG_USER1 register.

1b: Forced DCM operation during the soft-start ramp

5 SEL_NOC_TON R/W NVM Select the on-time for NOC operation. See for more details
4:3 SEL_LO_CS R/W NVM These bits select the LOUT (output inductor value) for the current sensing circuit.

00b: LOUT = 100 nH

01b: LOUT = 200 nH

10b: LOUT = 300 nH

11b: LOUT = 400 nH

2:0 DCLL R/W NVM These bits determine the DCLL setting.

000b: DCLL = 0 mΩ (VOUT maintains the regulation regardless of the load current)

001b: DCLL = 0.5 mΩ

010b: DCLL = 0.75 mΩ

011b: DCLL = 1.0 mΩ

100b: DCLL = 1.5 mΩ

101b: DCLL = 2.9 mΩ

110b: DCLL = 3.2 mΩ

111b: DCLL = 4.05 mΩ

Table 7-66 High-side On Time During a NOC Operation
PROTOCOL_ID in (C2h) PROTOCOL_ID_SVID SEL_NOC_TON Option tON_NOC (ns)
PROTOCOL_ID = 01b or 10b (VOUT step = 5 mV) 1 Shorter tON_NOC Use:
Equation 9. t O N _ N O C = 0.6   V P V I N × f S W
0 Longer tON_NOC Use:
Equation 10. t O N _ N O C = 1.6   V P V I N × f S W
PROTOCOL_ID = 00b or 11b (VOUT step = 10 mV) 1 Shorter tON_NOC Use:
Equation 11. t O N _ N O C = 1.2   V P V I N × f S W
0 Longer tON_NOC Use:
Equation 12. t O N _ N O C = 3.2   V P V I N × f S W