ZHCSQE8D November   2022  – November 2023 TPS389C03-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  I2C
      2. 7.3.2  Maskable Interrupt (AMSK)
      3. 7.3.3  VDD
      4. 7.3.4  MON
      5. 7.3.5  NRST
      6. 7.3.6  NIRQ
      7. 7.3.7  ADC
      8. 7.3.8  Packet Error Checking (PEC)
      9. 7.3.9  Q&A Watchdog
        1. 7.3.9.1 Question and Token Generation
        2. 7.3.9.2 Q&A Watchdog Open and Close Window Delay
        3. 7.3.9.3 Q&A Watchdog Status Register
        4. 7.3.9.4 Q&A Watchdog Timing
        5. 7.3.9.5 Q&A Watchdog State Machine and Test Program
      10. 7.3.10 Error Signal Monitoring (ESM)
        1. 7.3.10.1 ESM Timing
    4. 7.4 Device Functional Modes
      1. 7.4.1 Built-In Self Test and Configuration Load
        1. 7.4.1.1 Notes on BIST Execution
      2. 7.4.2 TPS389C03-Q1 Power ON
  9. 8 Register Maps
    1. 8.1 Registers Overview
      1. 8.1.1 BANK0 Registers
      2. 8.1.2 BANK1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Automotive Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supply Guidelines
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Documentation Support
    3. 10.3 接收文档更新通知
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 静电放电警告
    7. 10.7 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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7.3.7 ADC

The ADC used in the TPS389C03Q-1 runs on a 1MHz clock with an effective sampling rate of 1/8 MHz (= 125 kHz). Initially, the ADC records with a resolution of 12 bits (1LSB = 0.41667mV) which is later round off to 8-bit data for I2C transaction. (1LSB = 5mV) The ADC uses ping-pong architecture in which it requires 2us for both sampling and conversion per channel with a total of 2 sampling channels. While CH0 performs coarse conversion, CH1 does fine conversion and vice versa.

Digitized 8-bit data is updated once the fine conversion is completed, which occurs once every 8 μs. Each I2C transaction initiated for reading 8-bit MON_LVL data (the ADC data of a particular channel), 8-bit data is paused from updating until the I2C transaction completes.

Voltage scaling is done using a resistor ladder, but for differential mode channels, a chopping circuit is used to get the average of both of the voltages (VMON + VMON_RS)/2 since VMON_RS can be negative and can’t be converted into an ADC code. VMON – VMON_RS is calculated digitally by subtracting ((VMON + VMON_RS) /2) from VMON and then multiplying by 2.

The MONX channels can be configured in 1x (0.2V to 1.475V) or 4x mode (0.8V to 5.5V). For differential mode channels configured in 1x mode, (MON1 and MON2) the ADC range is limited up to 1.7V. To configure an ADC channel above 1.7 V, please use 4x mode.

Real time voltage measurements use.

Equation 1. Vlvl = ((ADC[7:0] * 5mV) + 0.2) * (VRANGE_MULT)
  1. ADC[7:0] is translated to a corresponding decimal value. The value of ADC[7:0] corresponding to MON2- MON4 can be read from BANK0, registers 0x41 to 0x43 found in Section 8.1.1.
  2. VRANGE_MULT corresponds to the selected monitor voltage multiplier set in BANK1, register 0x1F of Section 8.1.2.
  3. VRANGE_MULT is set to a decimal 1 or 4 value depending on monitored value.