ZHCSQV9A August 2022 – April 2024 TMDS1204
PRODUCTION DATA
This example assumes TMDS1204 transmitters are DC-coupled to the HDMI sink. In this example, TMDS1204 will be configured for linear mode with adaptive EQ enabled and TMDS1204 will automatically determine HDMI data rate by snooping DDC traffic between the HDMI source and sink.
// (address, data)
// Initial power-on configuration.
(0x0A, 0x00), // Rate snoop and TXFFE snoop enabled.
(0x0B, 0x23), // 3G and 6G slew rate control
(0x0C, 0x00), // HDMI clock tx slew rate control
(0x0D, 0xA3), // Linear mode, DC-coupled TX, 0dB DCG, Term fixed at 100Ω, disable CTLE bypass
(0x0E, 0x97), // HDMI14, 2.0 and 2.1 CTLE selection
(0x12, 0x03), // Clock lane VOD and TXFFE
(0x13, 0x00), // Clock lane EQ.
(0x14, 0x03), // D0 lane VOD and TXFFE.
(0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.
(0x16, 0x03), // D1 lane VOD and TXFFE.
(0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.
(0x18, 0x03), // D2 lane VOD and TXFFE.
(0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.
(0x1E, 0x40), // Enable AEQ
(0x09, 0x00), // Take out of PD state. Should be done after initialization is complete.