ZHCSQV9A August   2022  – April 2024 TMDS1204

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD and Latch-Up Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Feature Description
      1. 7.2.1  4-Level Inputs
      2. 7.2.2  I/O Voltage Level Selection
      3. 7.2.3  HPD_OUT
      4. 7.2.4  Lane Control
      5. 7.2.5  Swap
      6. 7.2.6  Linear and Limited Redriver
      7. 7.2.7  Main Link Inputs
      8. 7.2.8  Receiver Equalizer
      9. 7.2.9  CTLE Bypass
      10. 7.2.10 Adaptive Equalization in HDMI 2.1 FRL
        1. 7.2.10.1 HDMI 2.1 TX Compliance Testing with AEQ Enabled
      11. 7.2.11 HDMI 2.1 Link Training Compatible Rx EQ
      12. 7.2.12 Input Signal Detect
        1. 7.2.12.1 SIGDET_OUT Indicator
      13. 7.2.13 Main Link Outputs
        1. 7.2.13.1 Transmitter Bias
        2. 7.2.13.2 Transmitter Impedance Control
        3. 7.2.13.3 TX Slew Rate Control
        4. 7.2.13.4 TX Pre-Emphasis and De-Emphasis Control
        5. 7.2.13.5 TX Swing Control
        6. 7.2.13.6 Fan-out Buffer
      14. 7.2.14 HDMI DDC Capacitance
      15. 7.2.15 DisplayPort
    3. 7.3 Device Functional Modes
      1. 7.3.1 MODE Control
        1. 7.3.1.1 I2C Mode (MODE = "F")
        2. 7.3.1.2 Pin Strap Modes
          1. 7.3.1.2.1 Pin-Strap: HDMI 1.4 and HDMI 2.0 Functional Description
          2. 7.3.1.2.2 Pin-Strap HDMI 2.1 Function (MODE = "0"): Fixed Rx EQ)
          3. 7.3.1.2.3 Pin-Strap HDMI 2.1 Function (Mode = "1"): Flexible Rx EQ
          4. 7.3.1.2.4 Pin-Strap HDMI 2.1 Function (Mode = "R"): Flexible Rx EQ and Fan-Out Buffer
      2. 7.3.2 DDC Snoop Feature
        1. 7.3.2.1 HDMI Type
        2. 7.3.2.2 HDMI 2.1 FRL Snoop
      3. 7.3.3 Low Power States
    4. 7.4 Programming
      1. 7.4.1 Pseudocode Examples
        1. 7.4.1.1 HDMI 2.1 Source Example with DDC Snoop Disabled and DDC Buffer Disabled
        2. 7.4.1.2 Sink Example
      2. 7.4.2 TMDS1204 I2C Address Options
      3. 7.4.3 I2C Target Behavior
    5. 7.5 Register Maps
      1. 7.5.1 TMDS1204 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Source-Side Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Pre-Channel (LAB)
        2. 8.2.2.2 Post-Channel (LCD)
        3. 8.2.2.3 Common Mode Choke
        4. 8.2.2.4 ESD Protection
      3. 8.2.3 Application Curves
    3. 8.3 Typical Sink-Side Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedures
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Supply Decoupling
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 器件和文档支持
    1. 9.1 文档支持
      1. 9.1.1 相关文档
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 商标
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.4.3 I2C Target Behavior

GUID-E13B7B81-8E71-437A-8B16-3378628DDD48-low.svgFigure 7-5 I2C Write with Data

The following procedure should be followed to write data to TMDS1204 I2C registers (refer to Figure 7-5):

  1. The controller initiates a write operation by generating a start condition (S), followed by the TMDS1204 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The TMDS1204 acknowledges the address cycle.
  3. The controller presents the register offset within TMDS1204 to be written, consisting of one byte of data, MSB-first.
  4. The TMDS1204 acknowledges the sub-address cycle.
  5. The controller presents the first byte of data to be written to the I2C register.
  6. The TMDS1204 acknowledges the byte transfer.
  7. The controller may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the TMDS1204.
  8. The controller terminates the write operation by generating a stop condition (P).

GUID-559A0859-09BE-4579-9037-5B5CC163145D-low.svgFigure 7-6 I2C Read Without Repeated Start

The following procedure should be followed to read the TMDS1204 I2C registers without a repeated Start (refer to Figure 7-6).

  1. The controller initiates a read operation by generating a start condition (S), followed by the TMDS1204 7-bit address and a zero-value “W/R” bit to indicate a read cycle.
  2. The TMDS1204 acknowledges the 7-bit address cycle.
  3. Following the acknowledge the controller continues sending clock.
  4. The TMDS1204 transmit the contents of the memory registers MSB-first starting at register 00h or last read register offset+1. If a write to the I2C register occurred prior to the read, then the TMDS1204 shall start at the register offset specified in the write.
  5. The TMDS1204 waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the controller after each byte transfer; the I2C controller acknowledges reception of each data byte transfer.
  6. If an ACK is received, then the TMDS1204 transmits the next byte of data as long as controller provides the clock. If a NAK is received, then the TMDS1204 stops providing data and waits for a stop condition (P).
  7. The controller terminates the write operation by generating a stop condition (P).

GUID-FE9A707A-5D0B-4845-A5B0-143D807384E0-low.svgFigure 7-7 I2C Read with Repeated Start

The following procedure should be followed to read the TMDS1204 I2C registers with a repeated Start (refer to Figure 7-7).

  1. The controller initiates a read operation by generating a start condition (S), followed by the TMDS1204 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The TMDS1204 acknowledges the 7-bit address cycle.
  3. The controller presents the register offset within TMDS1204 to be written, consisting of one byte of data, MSB-first.
  4. The TMDS1204 acknowledges the register offset cycle.
  5. The controller presents a repeated start condition (Sr).
  6. The controller initiates a read operation by generating a start condition (S), followed by the TMDS1204 7-bit address and a one-value “W/R” bit to indicate a read cycle.
  7. The TMDS1204 acknowledges the 7-bit address cycle.
  8. The TMDS1204 transmit the contents of the memory registers MSB-first starting at the register offset.
  9. The TMDS1204 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the controller after each byte transfer; the I2C controller acknowledges reception of each data byte transfer.
  10. If an ACK is received, then the TMDS1204 transmits the next byte of data as long as controller provides the clock. If a NAK is received, then the TMDS1204 stops providing data and waits for a stop condition (P).
  11. The controller terminates the read operation by generating a stop condition (P).

GUID-D51F023E-31C2-46FB-ADA0-793F5818A854-low.svgFigure 7-8 I2C Write Without Data

The following procedure should be followed for setting a starting sub-address for I2C reads (refer to Figure 7-8).

  1. The controller initiates a write operation by generating a start condition (S), followed by the TMDS1204 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The TMDS1204 acknowledges the address cycle.
  3. The controller presents the register offset within TMDS1204 to be written, consisting of one byte of data, MSB-first.
  4. The TMDS1204 acknowledges the register offset cycle.
  5. The controller terminates the write operation by generating a stop condition (P).

Note: Figure 7-6 that if no register offset is included for the read procedure after initial power-up, then reads start at register offset 00h and continue byte by byte through the registers until the I2C controller terminates the read operation. During a read operation, the TMDS1204 auto-increments the I2C internal register address of the last byte transferred independent of whether or not an ACK was received from the I2C controller.