6 Parameter Measurement Information

Figure 6-1 Power-On Timing Requirements

Figure 6-2 TMDS Main Link Test Circuit

Figure 6-3 Input or Output Timing Measurements

Figure 6-4 Output Differential Waveform

Figure 6-5 Output Differential Waveform with De-Emphasis

(1) The FR4 trace between TTP1 and TTP2 is designed to emulate 1-12” of FR4, AC-coupling capacitor, connector and another 2” of FR4. Trace width – 4 mils. 100 Ω differential impedance.

(2) All Jitter is measured at a BER of 10⁹. HDMI 2.1 jitter measured at BER 10^-10.

(3) Residual jitter reflects the total jitter measured at TTP4 minus the jitter measured at TTP

(4) AVCC = 3.3V.

(5) R_T = 50 Ω.

(6) For HDMI 1.4 or 2.0, the input signal from parallel Bert does not have any pre-emphasis or de-emphasis. For HDMI 2.1 FRL, the input signal from BERT will have 2.18dB pre-shoot and −3.1dB de-emphasis. Refer to Recommended Operating Conditions.

Figure 6-6 HDMI Output Jitter Measurement

Figure 6-7 HPD Logic Shutdown and Propagation Timing

Figure 6-8 HPD Logic Standby and Propagation Timing

Figure 6-9 I²C SCL and SDA Timing

Figure 6-10 V_ID(DC) and V_ID(EYE)