ZHCSMZ5D April   2020  – January 2023 TLV841

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 VDD Hysteresis
        2. 8.3.1.2 VDD Transient Immunity
      2. 8.3.2 SENSE Input (TLV841S)
        1. 8.3.2.1 SENSE Hysteresis
        2. 8.3.2.2 Immunity to SENSE Pin Voltage Transients
      3. 8.3.3 User-Programmable Reset Time Delay for TLV841C only
      4. 8.3.4 Manual Reset (MR) Input for TLV841M only
      5. 8.3.5 Output Logic
        1. 8.3.5.1 RESET Output, Active-Low
        2. 8.3.5.2 RESET Output, Active-High
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VPOR)
      2. 8.4.2 Below Power-On-Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves: TLV841EVM
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 Trademarks
    6. 12.6 静电放电警告
    7. 12.7 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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7.7 Timing Diagrams

A. Open-Drain timing diagram assumes the RESET pin is connected via an external pull-up resistor to VDD.
Figure 7-1 Timing Diagram for TLV841SxxL (SENSE) Active Low Output
[Open-Drain and Push-Pull Output Topology]
A. Open-Drain timing diagram assumes the RESET pin is connected via an external pull-up resistor to VDD.
Figure 7-2 Timing Diagram for TLV841SxxH (SENSE) Active High Output
[Open-Drain and Push-Pull Output Topology]
A. Open-Drain timing diagram assumes the RESET / RESET pin is connected via an external pull-up resistor to VDD.
B. tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to CT pin then tD programmed time will be added to the startup time, VDD slew rate = 1 V / µs.
C. Be advised that the VDD falling slew rate is (slew rate > 1 V / µs) and resulting RESETin what is shown above figure. The RESET behavior would be similar to #T5037184-71 if the slew rate was much slower or if VDD decay time is larger than the prop delay (tD_HL).
Figure 7-3 Timing Diagram for TLV841CxxL (CT) Active Low Output
[Open-Drain and Push-Pull Output Topology]
A. Open-Drain timing diagram assumes the RESET / RESET pin is connected via an external pull-up resistor to VDD.
Figure 7-4 Timing Diagram for TLV841MxxL Active Low Output (MR)
[Open-Drain and Push-Pull Output Topology]