ZHCSO75A June 2021 – November 2021 TAS6424E-Q1
PRODUCTION DATA
The Miscellaneous Control 5 register is shown in and described in Table 9-41.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SS_BW_SEL | SS_DIV2 | PHASE_SEL | RESERVED | ||||
R/W-0 | R/W-0 | R/W-0 | R/W-01010 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SS_BW_SEL | R/W | 0 | Spread Spectrum Bandwidth Selection. Must be set to "1" when Spread Spectrum is enabled. 0: Spread Spectrum disabled 1: Spread Spectrum enabled |
6 | SS_DIV2 | R/W | 0 | Spread Spectrum Post Divider Control. Must be set to "1" when Spread Spectrum is enabled. 0: Spread Spectrum disabled 1: Spread Spectrum enabled |
5 | PHASE_SEL | R/W | 0 | WARNING: This bit must be set to '1' before exiting STANDBY. By default, this bit is set to '0', which is an output stage phase option not supported by this device. 0: RESERVED (default, must be changed to '1') 1: Supported Phase Offsets |
4-0 | RESERVED | R/W | 01010 | RESERVED |