ZHCSMY2 December   2020 PCM6480-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: I2C Interface
    7. 7.7  Switching Characteristics: I2C Interface
    8. 7.8  Timing Requirements: SPI Interface
    9. 7.9  Switching Characteristics: SPI Interface
    10. 7.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 7.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 7.12 Timing Requirements: PDM Digital Microphone Interface
    13. 7.13 Switching Characteristics: PDM Digial Microphone Interface
    14. 7.14 Timing Diagrams
    15. 7.15 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Serial Interfaces
        1. 8.3.1.1 Control Serial Interfaces
        2. 8.3.1.2 Audio Serial Interfaces
          1. 8.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 8.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 8.3.1.2.3 Left-Justified (LJ) Interface
        3. 8.3.1.3 Using Multiple Devices With Shared Buses
      2. 8.3.2  Phase-Locked Loop (PLL) and Clock Generation
      3. 8.3.3  Analog Input Channel Configuration
      4. 8.3.4  Reference Voltage
      5. 8.3.5  Microphone Bias
      6. 8.3.6  Input DC Fault Diagnostics
        1. 8.3.6.1 Fault Conditions
          1. 8.3.6.1.1 Input Pin Short to Ground
          2. 8.3.6.1.2 Input Pin Short to MICBIAS
          3. 8.3.6.1.3 Open Inputs
          4. 8.3.6.1.4 Short Between INxP and INxM
          5. 8.3.6.1.5 Input Pin Overvoltage
          6. 8.3.6.1.6 Input Pin Short to VBAT_IN
        2. 8.3.6.2 Fault Reporting
          1. 8.3.6.2.1 Overcurrent and Overtemperature Protection
      7. 8.3.7  Digital PDM Microphone Record Channel
      8. 8.3.8  Signal-Chain Processing
        1. 8.3.8.1 Programmable Channel Gain and Digital Volume Control
        2. 8.3.8.2 Programmable Channel Gain Calibration
        3. 8.3.8.3 Programmable Channel Phase Calibration
        4. 8.3.8.4 Programmable Digital High-Pass Filter
        5. 8.3.8.5 Programmable Digital Biquad Filters
        6. 8.3.8.6 Programmable Channel Summer and Digital Mixer
        7. 8.3.8.7 Configurable Digital Decimation Filters
          1. 8.3.8.7.1 Linear Phase Filters
            1. 8.3.8.7.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 8.3.8.7.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 8.3.8.7.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 8.3.8.7.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 8.3.8.7.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 8.3.8.7.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 8.3.8.7.1.7 Sampling Rate: 192 kHz or 176.4 kHz
            8. 8.3.8.7.1.8 Sampling Rate: 384 kHz or 352.8 kHz
            9. 8.3.8.7.1.9 Sampling Rate: 768 kHz or 705.6 kHz
          2. 8.3.8.7.2 Low-Latency Filters
            1. 8.3.8.7.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.8.7.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.8.7.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.8.7.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.8.7.2.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 8.3.8.7.2.6 Sampling Rate: 192 kHz or 176.4 kHz
          3. 8.3.8.7.3 Ultra-Low-Latency Filters
            1. 8.3.8.7.3.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.8.7.3.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.8.7.3.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.8.7.3.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.8.7.3.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 8.3.8.7.3.6 Sampling Rate: 192 kHz or 176.4 kHz
            7. 8.3.8.7.3.7 Sampling Rate: 384 kHz or 352.8 kHz
      9. 8.3.9  Automatic Gain Controller (AGC)
      10. 8.3.10 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 8.4 Device Functional Modes
      1. 8.4.1 Hardware Shutdown
      2. 8.4.2 Sleep Mode or Software Shutdown
      3. 8.4.3 Active Mode
      4. 8.4.4 Software Reset
    5. 8.5 Programming
      1. 8.5.1 Control Serial Interfaces
        1. 8.5.1.1 I2C Control Interface
          1. 8.5.1.1.1 General I2C Operation
          2. 8.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 8.5.1.1.2.1 I2C Single-Byte Write
            2. 8.5.1.1.2.2 I2C Multiple-Byte Write
            3. 8.5.1.1.2.3 I2C Single-Byte Read
            4. 8.5.1.1.2.4 I2C Multiple-Byte Read
        2. 8.5.1.2 SPI Control Interface
    6. 8.6 Register Maps
      1. 8.6.1 Device Configuration Registers
        1. 8.6.1.1 Registers Access Type
        2. 8.6.1.2 Page 0 Registers
        3. 8.6.1.3 Page 1 Registers
      2. 8.6.2 Programmable Coefficient Registers
        1. 8.6.2.1 Programmable Coefficient Registers: Page 2
        2. 8.6.2.2 Programmable Coefficient Registers: Page 3
        3. 8.6.2.3 Programmable Coefficient Registers: Page 4
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Four-Channel Analog Microphone and Four-Channel PDM Microphone Simultaneous Recording Using the PCM6480-Q1
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Example Device Register Configuration Script for EVM Setup
        3. 9.2.1.3 Application Curves
    3. 9.3 What To Do and What Not To Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 Trademarks
    6. 12.6 静电放电警告
    7. 12.7 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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订购信息

Input DC Fault Diagnostics

Each input of the PCM6480-Q1 features highly comprehensive DC fault diagnostics that can be configured to detect fault conditions in the DC-coupled input configuration and trigger an interrupt request to a host processor. Diagnostics are enabled for each channel by configuring DIAG_CFG0, P0_R100. For channels with diagnostics enabled, the input pins are scanned automatically by an integrated SAR ADC with a programmable repetition rate. The repetition rate can be configured using the REP_RATE, P0_R103_D7-6 register bits. For fastest fault response time and also to get better signal integrity and signal chain performance for the record channel, REP_RATE must be configured to 0 (non-default setting) . The diagnostic processor averages eight consecutive samples per test to improve noise performance. The DC fault diagnostics is not supported in the AC-coupled input configuration.

The device features various programmable threshold registers, P0_R101 to P0_R102, which can by configured by the host processor to define the fault region for a different category of fault condition detection. Additionally, there is also a debounce feature, configured with FAULT_DBNCE_SEL, P0_R103_D3-2. This feature sets the number of consecutive scan counts where the fault condition occurs before the latched status register is tripped, thus reducing false triggers by transient events. The device also has a moving average feature, P0_R104, which continuously averages out the newly measured data with old measured data and thus reduces the false triggers by any short-duration transient events.