ZHCSG67A March   2017  – December 2018 OPT3001-Q1


  1. 特性
  2. 应用
  3. 说明
    1.     框图
    2.     光谱响应:OPT3001-Q1 和人眼
  4. 修订历史记录
  5. 说明 (续)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Human Eye Matching
      2. 8.3.2 Automatic Full-Scale Range Setting
      3. 8.3.3 Interrupt Operation, INT Pin, and Interrupt Reporting Mechanisms
      4. 8.3.4 I2C Bus Overview
        1. Serial Bus Address
        2. Serial Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Automatic Full-Scale Setting Mode
      2. 8.4.2 Interrupt Reporting Mechanism Modes
        1. Latched Window-Style Comparison Mode
        2. Transparent Hysteresis-Style Comparison Mode
        3. End-of-Conversion Mode
        4. End-of-Conversion and Transparent Hysteresis-Style Comparison Mode
    5. 8.5 Programming
      1. 8.5.1 Writing and Reading
        1. High-Speed I2C Mode
        2. General-Call Reset Command
        3. SMBus Alert Response
    6. 8.6 Register Maps
      1. 8.6.1 Internal Registers
        1. Register Descriptions
          1. Result Register (offset = 00h)
            1. Table 7. Result Register Field Descriptions
          2. Configuration Register (offset = 01h) [reset = C810h]
            1. Table 10. Configuration Register Field Descriptions
          3. Low-Limit Register (offset = 02h) [reset = C0000h]
            1. Table 11. Low-Limit Register Field Descriptions
          4. High-Limit Register (offset = 03h) [reset = BFFFh]
            1. Table 13. High-Limit Register Field Descriptions
          5. Manufacturer ID Register (offset = 7Eh) [reset = 5449h]
            1. Table 14. Manufacturer ID Register Field Descriptions
          6. Device ID Register (offset = 7Fh) [reset = 3001h]
            1. Table 15. Device ID Register Field Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Electrical Interface
      2. 9.1.2 Optical Interface
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Optomechanical Design
        2. Dark Window Selection and Compensation
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13机械、封装和可订购信息
    1. 13.1 焊接和处理建议
    2. 13.2 DNP (S-PDSO-N6) 机械制图


机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

Writing and Reading

Accessing a specific register on the OPT3001-Q1 device is accomplished by writing the appropriate register address during the I2C transaction sequence. Refer to Table 6 for a complete list of registers and their corresponding register addresses. The value for the register address (as shown in Figure 23) is the first byte transferred after the slave address byte with the R/W bit low.

OPT3001-Q1 aij_I2CPointerWr.gif


The value of the slave address byte is determined by the ADDR pin setting; see Table 1.
Figure 23. Setting the I2C Register Address

Writing to a register begins with the first byte transmitted by the master. This byte is the slave address with the R/W bit low. The OPT3001-Q1 device then acknowledges receipt of a valid address. The next byte transmitted by the master is the address of the register that data are to be written to. The next two bytes are written to the register addressed by the register address. The OPT3001-Q1 device acknowledges receipt of each data byte. The master may terminate the data transfer by generating a start or stop condition.

When reading from the OPT3001-Q1 device, the last value stored in the register address by a write operation determines which register is read during a read operation. To change the register address for a read operation, a new partial I2C write transaction must be initiated. This partial write is accomplished by issuing a slave address byte with the R/W bit low, followed by the register address byte and a stop command. The master then generates a start condition and sends the slave address byte with the R/W bit high to initiate the read command. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the register address. This byte is followed by an acknowledge from the master; then the slave transmits the least significant byte. The master acknowledges receipt of the data byte. The master may terminate the data transfer by generating a not-acknowledge after receiving any data byte, or by generating a start or stop condition. If repeated reads from the same register are desired, continually sending the register address bytes is not necessary; the OPT3001-Q1 device retains the register address until that number is changed by the next write operation.

Figure 24 and Figure 25 show the write and read operation timing diagrams, respectively. Note that register bytes are sent most significant byte first, followed by the least significant byte.

OPT3001-Q1 aij_I2CWrite.gif


The value of the slave address byte is determined by the setting of the ADDR pin; see Table 1.
Figure 24. I2C Write Example
OPT3001-Q1 aij_I2CRead.gif


The value of the slave address byte is determined by the ADDR pin setting; see Table 1.


An ACK by the master can also be sent.
Figure 25. I2C Read Example