ZHCSG67A March 2017 – December 2018 OPT3001-Q1
To communicate with the OPT3001-Q1 device, the master must first initiate an I2C start command. Then, the master must address slave devices via a slave address byte. The slave address byte consists of seven address bits and a direction bit that indicates whether the action is to be a read or write operation.
Four I2C addresses are possible by connecting the ADDR pin to one of four pins: GND, VDD, SDA, or SCL. Table 1 summarizes the possible addresses with the corresponding ADDR pin configuration. The state of the ADDR pin is sampled on every bus communication and must be driven or connected to the desired level before any activity on the interface occurs.
|DEVICE I2C ADDRESS||ADDR PIN|