ZHCSG67A March 2017 – December 2018 OPT3001-Q1
The OPT3001-Q1 device offers compatibility with both I2C and SMBus interfaces. The I2C and SMBus protocols are essentially compatible with one another. The I2C interface is used throughout this document as the primary example with the SMBus protocol specified only when a difference between the two protocols is discussed.
The OPT3001-Q1 device is connected to the bus with two pins: an SCL clock input pin and an SDA open-drain bidirectional data pin. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates start and stop conditions. To address a specific device, the master initiates a start condition by pulling the data signal line (SDA) from a high logic level to a low logic level while SCL is high. All slaves on the bus shift in the slave address byte on the SCL rising edge, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by generating an acknowledge bit by pulling SDA low.
Data transfer is then initiated and eight bits of data are sent, followed by an acknowledge bit. During data transfer, SDA must remain stable while SCL is high. Any change in SDA while SCL is high is interpreted as a start or stop condition. When all data are transferred, the master generates a stop condition, indicated by pulling SDA from low to high while SCL is high. The OPT3001-Q1 device includes a 28-ms timeout on the I2C interface to prevent locking up the bus. If the SCL line is held low for this duration of time, the bus state machine is reset.