ZHCSG67A March 2017 – December 2018 OPT3001-Q1
An end-of-conversion indicator mode can be used when every measurement is desired to be read by the processor, prompted by the INT pin going active on every measurement completion. This mode is entered by setting the most significant two bits of the low-limit register (LE[3:2] from the Low-Limit Register) to 11b. This end-of-conversion mode is typically used in conjunction with the latched window-style comparison mode. The INT pin becomes inactive when the configuration register is read or the configuration register is written with a non-shutdown parameter or in response to an SMBus alert response. Table 4 summarizes the interrupt reporting mechanisms as a result of various operations.
|OPERATION||FLAG HIGH FIELD||FLAG LOW FIELD||INT PIN(1)||CONVERSION READY FIELD|
|The result register is above the high-limit register for fault count times. See the Result Register and the High-Limit Register for further details.||1||X||Active||1|
|The result register is below the low-limit register for fault count times. See the Result Register and the Low-Limit Register for further details.||X||1||Active||1|
|The conversion is complete with fault count criterion not met||X||X||Active||1|
|Configuration register read(3)||0||0||Inactive||0|
|Configuration register write, M[1:0] = 00b (shutdown)||X||X||X||X|
|Configuration register write, M[1:0] > 00b (not shutdown)||X||X||X||0|
|SMBus alert response protocol||X||X||Inactive||X|
Note that when transitioning from end-of-conversion mode to the standard comparison modes (that is, programming LE[3:2] from 11b to 00b) while the configuration register latch field (L) is 1, a subsequent write to the configuration register latch field (L) to 0 is necessary in order to properly clear the INT pin. The latch field can then be set back to 1 if desired.