ZHCSR47C October 2022 – January 2024 MSPM0L1105 , MSPM0L1106
PRODUCTION DATA
请参考 PDF 数据表获取器件具体的封装图。
表 6-1 介绍了每个器件封装中每个引脚上可用的功能。
PINCMx | 引脚功能 | 引脚编号 | I/O 结构 | |||||||
---|---|---|---|---|---|---|---|---|---|---|
引脚名称 |
模拟 | 数字(1) | 32 VQFN | 28 VSSOP | 24 VQFN | 20 VSSOP | 16 WQFN | 16 SOT | ||
不适用 | VDD | 4 | 7 | 3 | 6 | 6 | 5 | 电源 | ||
不适用 | VSS | 5 | 8 | 4 | 7 | 7 | 6 | 电源 | ||
不适用 | VCORE | 32 | 3 | 23 | 3 | 3 | 2 | Power | ||
1 | PA0 | UART1_TX [2] / I2C0_SDA [3] / TIMG1_C0 [4] / SPI0_CS1 [5](默认 BSL I2C_SDA) | 1 | 4 | 24 | 4 | 4 | 3 | 5V 容限开漏 | |
2 | PA1 | UART1_RX [2] / I2C0_SCL [3] / TIMG1_C1 [4](默认 BSL I2C_SCL) | 2 | 5 | 1 | 5 | 5 | 4 | 5V 容限开漏 | |
不适用 | NRST | 3 | 6 | 2 | 复位(2) | |||||
3 | PA2 | ROSC | TIMG1_C1 [2] / SPI0_CS0 [3] | 6 | 9 | 5 | 8 | 8 | 7 | 标准 |
4 | PA3 | TIMG2_C0 [2] / SPI0_CS1 [3] / UART1_CTS [4] | 7 | 10 | 6 | - | - | - | 标准 | |
5 | PA4 | TIMG2_C1 [2] / SPI0_POCI [3] / UART1_RTS [4] | 8 | 11 | 7 | 9 | – | - | 标准 | |
6 | PA5 | TIMG0_C0 [2]/SPI0_PICO [3]/FCC_IN[4] | 9 | 12 | - | - | 9 | – | 高速 | |
7 | PA6 | TIMG0_C1 [2] / SPI0_SCK [3] | 10 | 13 | - | 10 | 10 | 8 | 标准 | |
8 | PA7 | CLK_OUT [3] / TIMG1_C0 [4] | 11 | – | - | - | - | - | 标准 | |
9 | PA8 | UART0_TX [2] / SPI0_CS0 [3] / UART1_RTS [4] / TIMG2_C0 [5] | 12 | - | - | - | - | - | 标准 | |
10 | PA9 | UART0_RX [2] / SPI0_PICO [3] / UART1_CTS [4] / TIMG2_C1 [5] | 13 | 14 | 8 | – | - | - | 标准 | |
11 | PA10 | UART1_TX [2] / SPI0_POCI [3] / I2C0_SDA [4] / TIMG4_C0 [5] | 14 | 15 | 9 | – | 11 | – | 高速 | |
12 | PA11 | UART1_RX [2] / SPI0_SCK [3] / I2C0_SCL [4] / TIMG4_C1 [5] | 15 | 16 | 10 | 11 | – | - | 标准 | |
13 | PA12 | UART0_CTS [2]/TIMG0_C0 [3]/FCC_IN[4] | 16 | – | - | - | - | - | 标准 | |
14 | PA13 | UART0_RTS [2] / TIMG0_C1 [3] / UART1_RX [4] | 17 | - | - | - | - | - | 标准 | |
15 | PA14 | UART1_CTS [2] / CLK_OUT [3] / UART1_TX [4] / TIMG1_C0 [5] | 18 | 17 | - | - | - | - | 标准 | |
16 | PA15 | A9 | UART1_RTS [2] / SPI0_CS2 [4] / TIMG4_C1 [5] | 19 | 18 | 11 | – | 12 | - | 标准 |
17 | PA16 | A8 | SPI0_POCI [4]/TIMG0_C0 [5]/FCC_IN[6] | 20 | 19 | 12 | 12 | 13 | - | 标准 |
18 | PA17 | UART0_TX [2] / SPI0_SCK [4] / TIMG4_C0 [5] / SPI0_CS1 [6] | 21 | 20 | 13 | 13 | - | 9 | 具有唤醒功能的标准配置 | |
19 | PA18 | A7 / GPAMP_IN- | UART0_RX [2] / SPI0_PICO [3] / TIMG4_C1 [5] (BSL 调用) | 22 | 21 | 14 | 14 | 14 | 10 | 具有唤醒功能的标准配置 |
20 | PA19 | SWDIO [2] / SPI0_POCI [4] | 23 | 22 | 15 | 15 | 15 | 11 | 高速 | |
21 | PA20 | A6 | SWCLK [2] / TIMG4_C0 [4] | 24 | 23 | 16 | 16 | 16 | 12 | 标准 |
22 | PA21 | A5 / VREF- | TIMG2_C0 [2] / UART0_CTS [3] / UART0_TX [4] | 25 | 24 | 17 | - | - | - | 标准 |
23 | PA22 | A4 / GPAMP_OUT | UART0_RX [2] / TIMG2_C1 [3] / UART0_RTS [4] / CLK_OUT [5] / UART1_RX [6](默认 BSL UART_RX) | 26 | 25 | 18 | 17 | 1 | 13 | 标准 |
24 | PA23 | VREF+ | UART0_TX [2] / SPI0_CS3 [3] / TIMG0_C0 [4] / UART0_CTS [5] / UART1_TX [6](默认 BSL UART_TX) | 27 | 26 | 19 | 18 | 2 | 14 | 标准 |
25 | PA24 | A3 | SPI0_CS2 [2] / TIMG0_C1 [3] / UART0_RTS [4] | 28 | 27 | 20 | 19 | – | 15 | 标准 |
26 | PA25 | A2 | TIMG4_C1 [2] / UART0_TX [3] / SPI0_PICO [4] | 29 | 28 | 21 | 20 | 2 | 16 | 标准 |
27 | PA26 | A1 / GPAMP_IN+ | TIMG1_C0 [2] / UART0_RX [3] / SPI0_POCI [4] | 30 | 1 | 22 | 1 | - | 1 | 标准 |
28 | PA27 | A0 | TIMG1_C1 [2] / SPI0_CS3 [3] | 31 | 2 | - | 2 | – | - | 标准 |
IO 结构 | 反转控制 | 驱动强度控制 | 迟滞控制 | 上拉电阻器 | 下拉电阻器 | 唤醒逻辑 |
---|---|---|---|---|---|---|
标准驱动 | 是 | 是 | 是 | |||
带唤醒功能的标准驱动 | 是 | 是 | 是 | 是 | ||
高速 | 是 | 是 | 是 | 是 | ||
5V 容限开漏 | 是 | 是 | 是 | 是 |