ZHCSGO9C June   2017  – September 2018 MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-2 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics, Active Mode Supply Currents
    6. 5.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
    10. 5.10 Typical Characteristics, Low-Power Mode Supply Currents
    11. 5.11 Typical Characteristics, Current Consumption per Module
    12. 5.12 Thermal Resistance Characteristics for 100-Pin LQFP (PZ) Package
    13. 5.13 Timing and Switching Characteristics
      1. 5.13.1  Power Supply Sequencing
        1. Table 5-1 Brownout and Device Reset Power Ramp Requirements
        2. Table 5-2 SVS
      2. 5.13.2  Reset Timing
        1. Table 5-3 Reset Input
      3. 5.13.3  Clock Specifications
        1. Table 5-4 Low-Frequency Crystal Oscillator, LFXT
        2. Table 5-5 High-Frequency Crystal Oscillator, HFXT
        3. Table 5-6 DCO
        4. Table 5-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 5-8 Module Oscillator (MODOSC)
      4. 5.13.4  Wake-up Characteristics
        1. Table 5-9  Wake-up Times From Low-Power Modes and Reset
        2. Table 5-10 Typical Wake-up Charges
        3. 5.13.4.1   Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 5.13.5  Digital I/Os
        1. Table 5-11 Digital Inputs
        2. Table 5-12 Digital Outputs
        3. 5.13.5.1   Typical Characteristics, Digital Outputs
      6. 5.13.6  LEA
        1. Table 5-13 Low-Energy Accelerator (LEA) Performance
      7. 5.13.7  Timer_A and Timer_B
        1. Table 5-14 Timer_A
        2. Table 5-15 Timer_B
      8. 5.13.8  eUSCI
        1. Table 5-16 eUSCI (UART Mode) Clock Frequency
        2. Table 5-17 eUSCI (UART Mode) Switching Characteristics
        3. Table 5-18 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-19 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 5-20 eUSCI (SPI Slave Mode) Switching Characteristics
        6. Table 5-21 eUSCI (I2C Mode) Switching Characteristics
      9. 5.13.9  Segment LCD Controller
        1. Table 5-22 LCD_C Recommended Operating Conditions
        2. Table 5-23 LCD_C Electrical Characteristics
      10. 5.13.10 ADC12_B
        1. Table 5-24 12-Bit ADC, Power Supply and Input Range Conditions
        2. Table 5-25 12-Bit ADC, Timing Parameters
        3. Table 5-26 12-Bit ADC, Linearity Parameters
        4. Table 5-27 12-Bit ADC, Dynamic Performance With External Reference
        5. Table 5-28 12-Bit ADC, Dynamic Performance With Internal Reference
        6. Table 5-29 12-Bit ADC, Temperature Sensor and Built-In V1/2
        7. Table 5-30 12-Bit ADC, External Reference
      11. 5.13.11 Reference
        1. Table 5-31 REF, Built-In Reference
      12. 5.13.12 Comparator
        1. Table 5-32 Comparator_E
      13. 5.13.13 FRAM
        1. Table 5-33 FRAM
      14. 5.13.14 USS
        1. Table 5-34 USS Recommended Operating Conditions
        2. Table 5-35 USS LDO
        3. Table 5-36 USSXTAL
        4. Table 5-37 USS HSPLL
        5. Table 5-38 USS SDHS
        6. Table 5-39 USS PHY Output Stage
        7. Table 5-40 USS PHY Input Stage, Multiplexer
        8. Table 5-41 USS PGA
        9. Table 5-42 USS Bias Voltage Generator
      15. 5.13.15 Emulation and Debug
        1. Table 5-43 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Ultrasonic Sensing Solution (USS) Module
    4. 6.4  Low-Energy Accelerator (LEA) for Signal Processing
    5. 6.5  Operating Modes
      1. 6.5.1 Peripherals in Low-Power Modes
      2. 6.5.2 Idle Currents of Peripherals in LPM3 and LPM4
    6. 6.6  Interrupt Vector Table and Signatures
    7. 6.7  Bootloader (BSL)
    8. 6.8  JTAG Operation
      1. 6.8.1 JTAG Standard Interface
      2. 6.8.2 Spy-Bi-Wire (SBW) Interface
    9. 6.9  FRAM Controller A (FRCTL_A)
    10. 6.10 RAM
    11. 6.11 Tiny RAM
    12. 6.12 Memory Protection Unit (MPU) Including IP Encapsulation
    13. 6.13 Peripherals
      1. 6.13.1  Digital I/O
      2. 6.13.2  Oscillator and Clock System (CS)
      3. 6.13.3  Power-Management Module (PMM)
      4. 6.13.4  Hardware Multiplier (MPY)
      5. 6.13.5  Real-Time Clock (RTC_C)
      6. 6.13.6  Measurement Test Interface (MTIF)
      7. 6.13.7  Watchdog Timer (WDT_A)
      8. 6.13.8  System Module (SYS)
      9. 6.13.9  DMA Controller
      10. 6.13.10 Enhanced Universal Serial Communication Interface (eUSCI)
      11. 6.13.11 TA0, TA1, and TA4
      12. 6.13.12 TA2 and TA3
      13. 6.13.13 TB0
      14. 6.13.14 ADC12_B
      15. 6.13.15 USS
      16. 6.13.16 Comparator_E
      17. 6.13.17 CRC16
      18. 6.13.18 CRC32
      19. 6.13.19 AES256 Accelerator
      20. 6.13.20 True Random Seed
      21. 6.13.21 Shared Reference (REF)
      22. 6.13.22 LCD_C
      23. 6.13.23 Embedded Emulation
        1. 6.13.23.1 Embedded Emulation Module (EEM) (S Version)
        2. 6.13.23.2 EnergyTrace++ Technology
    14. 6.14 Input/Output Diagrams
      1. 6.14.1  Port Function Select Registers (PySEL1 , PySEL0)
      2. 6.14.2  Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
      3. 6.14.3  Port P1 (P1.2 to P1.7) Input/Output With Schmitt Trigger
      4. 6.14.4  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
      5. 6.14.5  Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
      6. 6.14.6  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      7. 6.14.7  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      8. 6.14.8  Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      9. 6.14.9  Port P6 (P6.0) Input/Output With Schmitt Trigger
      10. 6.14.10 Port P6 (P6.1 to P6.5) Input/Output With Schmitt Trigger
      11. 6.14.11 Port P6 (P6.6 and P6.7) Input/Output With Schmitt Trigger
      12. 6.14.12 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
      13. 6.14.13 Port P7 (P7.4) Input/Output With Schmitt Trigger
      14. 6.14.14 Port P7 (P7.5) Input/Output With Schmitt Trigger
      15. 6.14.15 Port P7 (P7.6 and P7.7) Input/Output With Schmitt Trigger
      16. 6.14.16 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
      17. 6.14.17 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger
      18. 6.14.18 Port P9 (P9.0 to P9.3) Input/Output With Schmitt Trigger
      19. 6.14.19 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
      20. 6.14.20 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
      21. 6.14.21 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
    15. 6.15 Device Descriptors (TLV)
    16. 6.16 Memory Map
      1. 6.16.1 Peripheral File Map
    17. 6.17 Identification
      1. 6.17.1 Revision Identification
      2. 6.17.2 Device Identification
      3. 6.17.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1  Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2  External Oscillator (HFXT and LFXT)
      3. 7.1.3  USS Oscillator (USSXT)
      4. 7.1.4  Transducer Connection to the USS Module
      5. 7.1.5  Charge Pump Control of Input Multiplexer
      6. 7.1.6  JTAG
      7. 7.1.7  Reset
      8. 7.1.8  Unused Pins
      9. 7.1.9  General Layout Recommendations
      10. 7.1.10 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC12_B Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Detailed Design Procedure
        4. 7.2.1.4 Layout Guidelines
      2. 7.2.2 LCD_C Peripheral
        1. 7.2.2.1 Partial Schematic
        2. 7.2.2.2 Design Requirements
        3. 7.2.2.3 Detailed Design Procedure
        4. 7.2.2.4 Layout Guidelines
  8. 8器件和文档支持
    1. 8.1 入门和下一步
    2. 8.2 器件命名规则
    3. 8.3 工具和软件
    4. 8.4 文档支持
    5. 8.5 相关链接
    6. 8.6 商标
    7. 8.7 静电放电警告
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

1.1 特性

  • 具有超低功耗的一流超声波水流量测量
    • 差分飞行时间 (dTOF) 精度小于 25ps
    • 高精度时间测量分辨率小于 5ps
    • 能够检测低流速（<1 升/小时）
    • 在每秒测量一次的频率下总体电流消耗大约为 3µA
  • 符合并超出 ISO 4064、OIML R49 和 EN 1434 精度标准
  • 能够直接与标准超声波传感器（高达 2.5MHz）连接
  • 集成模拟前端 – 超声波感应解决方案 (USS)
    • 可在不同频率下生成脉冲的可编程脉冲生成 (PPG)
    • 具有低阻抗 (4Ω) 输出驱动器的集成物理接口 (PHY)，可控制输入和输出通道
    • 具有高达 8Msps 输出数据速率的高性能高速 12 位 Σ-Δ ADC (SDHS)
    • 具有 –6.5dB 至 30.8dB 增益的可编程增益放大器 (PGA)
    • 输出范围为 68MHz 至 80MHz 的高性能锁相环 (PLL)
  • 计量测试接口 (MTIF)
    • 脉冲发生器和脉冲计数器
    • 高达 1016 次脉冲/秒 (p/s) 的脉冲率
    • 计数容量高达 65535（16 位）
    • 在 LPM3.5 下以 200nA（典型值）运行
  • 低能耗加速器 (LEA)
    • 独立于 CPU 运行
    • 与 CPU 共享 4KB RAM
    • 256 点高效复变 FFT：
      比 Arm®Cortex®-M0+ 内核快多达 40 倍
  • 嵌入式微控制器
    • 高达 16MHz 时钟频率的 16 位 RISC 架构
    • 3.6V 至 1.8V 的宽电源电压范围（最低电源电压受限于 SVS 电平，请参阅 SVS 规格）
  • 经优化的超低功耗模式
    • 工作模式：大约 120µA/MHz
    • 待机模式下的实时时钟 (RTC) (LPM3.5)：450nA (1)
    • 关断电流 (LPM4.5)：30nA
      • 1. RTC 由 3.7pF 晶振生成。
  • 铁电随机存取存储器 (FRAM)
    • 高达 256KB 的非易失性存储器
    • 超低功耗写入
    • 125ns 每个字的快速写入（4ms 内写入 64KB）
    • 统一标准存储器 = 单个空间内的程序 + 数据 + 存储
    • 1015 写入周期持久性
    • 抗辐射和非磁性
  • 智能数字外设
    • 32 位硬件乘法器 (MPY)
    • 6 通道内部直接存储器访问 (DMA)
    • 具备日历和报警功能的 RTC
    • 六个 16 位定时器，每个定时器具有多达七个捕捉/比较寄存器
    • 32 位和 16 位循环冗余校验 (CRC)
  • 高性能模拟
    • 16 通道模拟比较器
    • 12 位 SAR ADC，具有窗口比较器、内部基准和采样保持功能以及多达 16 条外部输入通道
    • 具有高达 264 段对比度控制的集成 LCD 驱动器
  • 多功能输入/输出端口
    • 可每位、每字节和每字访问（成对访问）
    • 所有端口上，从 LPM 中的边沿可选唤醒
    • 所有端口上可编程上拉和下拉
  • 代码安全性和加密
    • 128 位或 256 位高级加密标准 (AES) 安全加密和解密协处理器
    • 针对随机数生成算法的随机数种子
    • IP 封装防止对存储器进行外部访问
    • FRAM 可提供固有安全性优势
  • 增强型串行通信
    • 多达四个 eUSCI_A 串行通信端口
      • 支持自动波特率侦测的通用异步收发器 (UART)
      • IrDA 编码和解码
    • 多达两个 eUSCI_B 串行通信端口
      • 支持多从设备寻址的 I2C
    • 硬件通用异步收发器 (UART) 或 I2C 自举程序 (BSL)
  • 灵活时钟系统
    • 具有 10 个可选厂家调整频率的定频数控振荡器 (DCO)
    • 低功率低频内部时钟源 (VLO)
    • 32kHz 晶振 (LFXT)
    • 高频晶振 (HFXT)
  • 开发工具和软件（另请参阅工具和软件）
  • 器件比较 汇总了可用的器件型号和封装选项
  • 要获得完整的模块说明，请参见《MSP430FR58xx、MSP430FR59xx 和 MSP430FR6xx 系列用户指南》