ZHCSER2 数据表 | 德州仪器 TI.com.cn

ZHCSER2D May 2013 – October 2020 MSP430F5252 , MSP430F5253 , MSP430F5254 , MSP430F5255 , MSP430F5256 , MSP430F5257 , MSP430F5258 , MSP430F5259

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

RGC|64
- MPQF125F
ZQE|80
- MPBG269E

散热焊盘机械数据 (封装 | 引脚)

RGC|64
- QFND102O

订购信息

9.9.2 Port Mapping Controller

The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P4 (see Table 9-8).

Table 9-8 Port Mapping Mnemonics and Functions

VALUE	PxMAPy MNEMONIC	INPUT PIN FUNCTION	OUTPUT PIN FUNCTION
0	PM_NONE	None	DVSS
1	PM_CBOUT0	–	COMP_B output
1	PM_TB0CLK	TB0 clock input	–
2	PM_ADC10CLK	–	ADC10CLK
2	PM_DMAE0	DMAE0 input	–
3	PM_SVMOUT	–	SVM output
3	PM_TB0OUTH	TB0 high-impedance input TB0OUTH	–
4	PM_TB0CCR0A	TB0 CCR0 capture input CCI0A	TB0 CCR0 compare output Out0
5	PM_TB0CCR1A	TB0 CCR1 capture input CCI1A	TB0 CCR1 compare output Out1
6	PM_TB0CCR2A	TB0 CCR2 capture input CCI2A	TB0 CCR2 compare output Out2
7	PM_TB0CCR3A	TB0 CCR3 capture input CCI3A	TB0 CCR3 compare output Out3
8	PM_TB0CCR4A	TB0 CCR4 capture input CCI4A	TB0 CCR4 compare output Out4
9	PM_TB0CCR5A	TB0 CCR5 capture input CCI5A	TB0 CCR5 compare output Out5
10	PM_TB0CCR6A	TB0 CCR6 capture input CCI6A	TB0 CCR6 compare output Out6
11	PM_UCA1RXD	USCI_A1 UART RXD (direction controlled by USCI – input)
11	PM_UCA1SOMI	USCI_A1 SPI slave out master in (direction controlled by USCI)
12	PM_UCA1TXD	USCI_A1 UART TXD (direction controlled by USCI – output)
12	PM_UCA1SIMO	USCI_A1 SPI slave in master out (direction controlled by USCI)
13	PM_UCA1CLK	USCI_A1 clock input/output (direction controlled by USCI)
13	PM_UCB1STE	USCI_B1 SPI slave transmit enable (direction controlled by USCI)
14	PM_UCB1SOMI	USCI_B1 SPI slave out master in (direction controlled by USCI)
14	PM_UCB1SCL	USCI_B1 I²C clock (open drain and direction controlled by USCI)
15	PM_UCB1SIMO	USCI_B1 SPI slave in master out (direction controlled by USCI)
15	PM_UCB1SDA	USCI_B1 I²C data (open drain and direction controlled by USCI)
16	PM_UCB1CLK	USCI_B1 clock input/output (direction controlled by USCI)
16	PM_UCA1STE	USCI_A1 SPI slave transmit enable (direction controlled by USCI)
17	PM_CBOUT1	None	COMP_B output
18	PM_MCLK	None	MCLK
19	PM_RTCCLK	None	RTCCLK output
20	PM_UCA0RXD	USCI_A0 UART RXD (direction controlled by USCI – input)
20	PM_UCA0SOMI	USCI_A0 SPI slave out master in (direction controlled by USCI)
21	PM_UCA0TXD	USCI_A0 UART TXD (direction controlled by USCI – output)
21	PM_UCA0SIMO	USCI_A0 SPI slave in master out (direction controlled by USCI)
22	PM_UCA0CLK	USCI_A0 clock input/output (direction controlled by USCI)
22	PM_UCB0STE	USCI_B0 SPI slave transmit enable (direction controlled by USCI)
23	PM_UCB0SOMI	USCI_B0 SPI slave out master in (direction controlled by USCI)
23	PM_UCB0SCL	USCI_B0 I²C clock (open drain and direction controlled by USCI)
24	PM_UCB0SIMO	USCI_B0 SPI slave in master out (direction controlled by USCI)
24	PM_UCB0SDA	USCI_B0 I²C data (open drain and direction controlled by USCI)
25	PM_UCB0CLK	USCI_B0 clock input/output (direction controlled by USCI)
25	PM_UCA0STE	USCI_A0 SPI slave transmit enable (direction controlled by USCI)
26	PM_UCA3RXD	USCI_A3 UART RXD (direction controlled by USCI – input)
26	PM_UCA3SOMI	USCI_A3 SPI slave out master in (direction controlled by USCI)
27	PM_UCA3TXD	USCI_A3 UART TXD (direction controlled by USCI – output)
27	PM_UCA3SIMO	USCI_A3 SPI slave in master out (direction controlled by USCI)
28	PM_UCB3SIMO	USCI_B3 SPI slave in master out (direction controlled by USCI)
28	PM_UCB3SDA	USCI_B3 I²C data (open drain and direction controlled by USCI)
29	PM_UCB3SOMI	USCI_B3 SPI slave out master in (direction controlled by USCI)
29	PM_UCB3SCL	USCI_B3 I²C clock (open drain and direction controlled by USCI)
30	Reserved	Reserved
31 (0FFh)⁽¹⁾	PM_ANALOG	Disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals

(1) The value of the PM_ANALOG mnemonic is 0FFh. The port mapping registers are only 5 bits wide, and the upper bits are ignored, which results in a read value of 31.

Table 9-9 lists the default settings for all pins that support port mapping.

Table 9-9 Default Mapping

PIN	PxMAPy MNEMONIC	INPUT PIN FUNCTION
P4.0/P4MAP0	PM_UCB1STE/PM_UCA1CLK	USCI_B1 SPI slave transmit enable (direction controlled by USCI) USCI_A1 clock input/output (direction controlled by USCI)
P4.1/P4MAP1	PM_UCB1SIMO/PM_UCB1SDA	USCI_B1 SPI slave in master out (direction controlled by USCI) USCI_B1 I²C data (open drain and direction controlled by USCI)
P4.2/P4MAP2	PM_UCB1SOMI/PM_UCB1SCL	USCI_B1 SPI slave out master in (direction controlled by USCI) USCI_B1 I²C clock (open drain and direction controlled by USCI)
P4.3/P4MAP3	PM_UCB1CLK/PM_UCA1STE	USCI_A1 SPI slave transmit enable (direction controlled by USCI) USCI_B1 clock input/output (direction controlled by USCI)
P4.4/P4MAP4	PM_UCA1TXD/PM_UCA1SIMO	USCI_A1 UART TXD (Direction controlled by USCI – output) USCI_A1 SPI slave in master out (direction controlled by USCI)
P4.5/P4MAP5	PM_UCA1RXD/PM_UCA1SOMI	USCI_A1 UART RXD (Direction controlled by USCI – input) USCI_A1 SPI slave out master in (direction controlled by USCI)
P4.6/P4MAP6	PM_UCA3TXD/PM_UCA3SIMO	USCI_A3 UART TXD (Direction controlled by USCI – output) USCI_A3 SPI slave in master out (direction controlled by USCI)
P4.7/P4MAP7	PM_UCA3RXD/PM_UCA3SOMI	USCI_A3 UART RXD (Direction controlled by USCI – input) USCI_A3 SPI slave out master in (direction controlled by USCI)