ZHCSOS0C august   2021  – june 2023 MCF8316A

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  Device Interface Modes
        1. 7.3.2.1 Interface - Control and Monitoring
        2. 7.3.2.2 I2C Interface
      3. 7.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 7.3.3.1 Buck in Inductor Mode
        2. 7.3.3.2 Buck in Resistor mode
        3. 7.3.3.3 Buck Regulator with External LDO
        4. 7.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 7.3.3.5 Mixed Mode Buck Operation and Control
        6. 7.3.3.6 Buck Undervoltage Protection
        7. 7.3.3.7 Buck Overcurrent Protection
      4. 7.3.4  AVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate Control
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  SPEED Control
        1. 7.3.8.1 Analog-Mode Speed Control
        2. 7.3.8.2 PWM-Mode Speed Control
        3. 7.3.8.3 I2C based Speed Control
        4. 7.3.8.4 Frequency-Mode Speed Control
        5. 7.3.8.5 Speed Profiles
          1. 7.3.8.5.1 Linear Speed Profiles
          2. 7.3.8.5.2 Staircase Speed Profiles
          3. 7.3.8.5.3 Forward-Reverse Speed Profiles
      9. 7.3.9  Starting the Motor Under Different Initial Conditions
        1. 7.3.9.1 Case 1 – Motor is Stationary
        2. 7.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 7.3.10 Motor Start Sequence (MSS)
        1. 7.3.10.1 Initial Speed Detect (ISD)
        2. 7.3.10.2 Motor Resynchronization
        3. 7.3.10.3 Reverse Drive
          1. 7.3.10.3.1 Reverse Drive Tuning
        4. 7.3.10.4 Motor Start-up
          1. 7.3.10.4.1 Align
          2. 7.3.10.4.2 Double Align
          3. 7.3.10.4.3 Initial Position Detection (IPD)
            1. 7.3.10.4.3.1 IPD Operation
            2. 7.3.10.4.3.2 IPD Release Mode
            3. 7.3.10.4.3.3 IPD Advance Angle
          4. 7.3.10.4.4 Slow First Cycle Startup
          5. 7.3.10.4.5 Open loop
          6. 7.3.10.4.6 Transition from Open to Closed Loop
      11. 7.3.11 Closed Loop Operation
        1. 7.3.11.1 Closed Loop Acceleration/Deceleration Slew Rate
        2. 7.3.11.2 Speed PI Control
        3. 7.3.11.3 Current PI Control
        4. 7.3.11.4 Overmodulation
      12. 7.3.12 Motor Parameters
        1. 7.3.12.1 Motor Resistance
        2. 7.3.12.2 Motor Inductance
        3. 7.3.12.3 Motor Back-EMF constant
      13. 7.3.13 Motor Parameter Extraction Tool (MPET)
      14. 7.3.14 Anti-Voltage Surge (AVS)
      15. 7.3.15 Output PWM Switching Frequency
      16. 7.3.16 Active Braking
      17. 7.3.17 PWM Modulation Schemes
      18. 7.3.18 Dead Time Compensation
      19. 7.3.19 Motor Stop Options
        1. 7.3.19.1 Coast (Hi-Z) Mode
        2. 7.3.19.2 Recirculation Mode
        3. 7.3.19.3 Low-Side Braking
        4. 7.3.19.4 High-Side Braking
        5. 7.3.19.5 Active Spin-Down
        6. 7.3.19.6 Align Braking
      20. 7.3.20 FG Configuration
        1. 7.3.20.1 FG Output Frequency
        2. 7.3.20.2 FG Open-Loop and Lock Behavior
      21. 7.3.21 DC Bus Current Limit
      22. 7.3.22 Protections
        1. 7.3.22.1  VM Supply Undervoltage Lockout
        2. 7.3.22.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 7.3.22.3  BUCK Undervoltage Lockout (BUCK_UV)
        4. 7.3.22.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 7.3.22.5  Overvoltage Protection (OVP)
        6. 7.3.22.6  Overcurrent Protection (OCP)
          1. 7.3.22.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.22.6.2 OCP Automatic Retry (OCP_MODE = 01b)
          3. 7.3.22.6.3 OCP Report Only (OCP_MODE = 10b)
          4. 7.3.22.6.4 OCP Disabled (OCP_MODE = 11b)
        7. 7.3.22.7  Buck Overcurrent Protection
        8. 7.3.22.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 7.3.22.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.22.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.22.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.22.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE= 1xx1b)
        9. 7.3.22.9  Thermal Warning (OTW)
        10. 7.3.22.10 Thermal Shutdown (TSD)
        11. 7.3.22.11 Motor Lock (MTR_LCK)
          1. 7.3.22.11.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 7.3.22.11.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 7.3.22.11.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 7.3.22.11.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        12. 7.3.22.12 Motor Lock Detection
          1. 7.3.22.12.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.22.12.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 7.3.22.12.3 Lock3: No-Motor Fault (NO_MTR)
        13. 7.3.22.13 MPET Faults
        14. 7.3.22.14 IPD Faults
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF Functionality
      2. 7.5.2 SOX Output
      3. 7.5.3 Oscillator Source
        1. 7.5.3.1 External Clock Source
      4. 7.5.4 External Watchdog
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Operation
        3. 7.6.2.3 I2C Read Operation
        4. 7.6.2.4 Examples of MCF8316A I2C Communication Protocol Packets
        5. 7.6.2.5 Internal Buffers
        6. 7.6.2.6 CRC Byte Calculation
    7. 7.7 EEPROM (Non-Volatile) Register Map
      1. 7.7.1 Algorithm_Configuration Registers
      2. 7.7.2 Fault_Configuration Registers
      3. 7.7.3 Hardware_Configuration Registers
      4. 7.7.4 Internal_Algorithm_Configuration Registers
    8. 7.8 RAM (Volatile) Register Map
      1. 7.8.1 Fault_Status Registers
      2. 7.8.2 System_Status Registers
      3. 7.8.3 Device_Control Registers
      4. 7.8.4 Algorithm_Control Registers
      5. 7.8.5 Algorithm_Variables Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Application Curves
        1. 8.2.1.1 Motor startup
        2. 8.2.1.2 MPET
        3. 8.2.1.3 Dead time compensation
        4. 8.2.1.4 Auto handoff
        5. 8.2.1.5 Motor stop – recirculation mode
        6. 8.2.1.6 Anti voltage surge (AVS)
  10. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 支持资源
    2. 11.2 Trademarks
    3. 11.3 静电放电警告
    4. 11.4 术语表
  13. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.7.1 Algorithm_Configuration Registers

ALGORITHM_CONFIGURATION Registers lists the memory-mapped registers for the Algorithm_Configuration registers. All register offset addresses not listed in ALGORITHM_CONFIGURATION Registers should be considered as reserved locations and the register contents should not be modified.

Table 7-13 ALGORITHM_CONFIGURATION Registers
AddressAcronymRegister NameSection
80hISD_CONFIGISD ConfigurationISD_CONFIG Register (Address = 80h) [Reset = 00000000h]
82hREV_DRIVE_CONFIGReverse Drive ConfigurationREV_DRIVE_CONFIG Register (Address = 82h) [Reset = 00000000h]
84hMOTOR_STARTUP1Motor Startup Configuration 1MOTOR_STARTUP1 Register (Address = 84h) [Reset = 00000000h]
86hMOTOR_STARTUP2Motor Startup Configuration 2MOTOR_STARTUP2 Register (Address = 86h) [Reset = 00000000h]
88hCLOSED_LOOP1Closed Loop Configuration 1CLOSED_LOOP1 Register (Address = 88h) [Reset = 00000000h]
8AhCLOSED_LOOP2Closed Loop Configuration 2CLOSED_LOOP2 Register (Address = 8Ah) [Reset = 00000000h]
8ChCLOSED_LOOP3Closed Loop Configuration 3CLOSED_LOOP3 Register (Address = 8Ch) [Reset = 00000000h]
8EhCLOSED_LOOP4Closed Loop Configuration 4CLOSED_LOOP4 Register (Address = 8Eh) [Reset = X]
94hSPEED_PROFILES1Speed Profile Configuration 1SPEED_PROFILES1 Register (Address = 94h) [Reset = X]
96hSPEED_PROFILES2Speed Profile Configuration 2SPEED_PROFILES2 Register (Address = 96h) [Reset = X]
98hSPEED_PROFILES3Speed Profile Configuration 3SPEED_PROFILES3 Register (Address = 98h) [Reset = X]
9AhSPEED_PROFILES4Speed Profile Configuration 4SPEED_PROFILES4 Register (Address = 9Ah) [Reset = X]
9ChSPEED_PROFILES5Speed Profile Configuration 5SPEED_PROFILES5 Register (Address = 9Ch) [Reset = X]
9EhSPEED_PROFILES6Speed Profile Configuration 6SPEED_PROFILES6 Register (Address = 9Eh) [Reset = X]

Complex bit access types are encoded to fit into small table cells. Algorithm_Configuration Access Type Codes shows the codes that are used for access types in this section.

Table 7-14 Algorithm_Configuration Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.7.1.1 ISD_CONFIG Register (Address = 80h) [Reset = 00000000h]

ISD_CONFIG is shown in ISD_CONFIG Register and described in ISD_CONFIG Register Field Descriptions.

Return to the Summary Table.

Register to configure initial speed detect settings

Figure 7-55 ISD_CONFIG Register
3130292827262524
PARITYISD_ENBRAKE_ENHIZ_ENRVS_DR_ENRESYNC_ENFW_DRV_RESYN_THR
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
FW_DRV_RESYN_THRBRK_MODERESERVEDRESERVEDBRK_TIME
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
BRK_TIMEHIZ_TIMESTAT_DETECT_THR
R/W-0hR/W-0hR/W-0h
76543210
STAT_DETECT_THRREV_DRV_HANDOFF_THRREV_DRV_OPEN_LOOP_CURRENT
R/W-0hR/W-0hR/W-0h
Table 7-15 ISD_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30ISD_ENR/W0h ISD enable

0h = Disable

1h = Enable

29BRAKE_ENR/W0h Brake enable

0h = Disable

1h = Enable

28HIZ_ENR/W0h Hi-Z enable

0h = Disable

1h = Enable

27RVS_DR_ENR/W0h Reverse drive enable

0h = Disable

1h = Enable

26RESYNC_ENR/W0h Resynchronization enable

0h = Disable

1h = Enable

25-22FW_DRV_RESYN_THRR/W0h Minimum speed threshold to resynchronize to close loop (% of MAX_SPEED)

0h = 5%

1h = 10%

2h = 15%

3h = 20%

4h = 25%

5h = 30%

6h = 35%

7h = 40%

8h = 45%

9h = 50%

Ah = 55%

Bh = 60%

Ch = 70%

Dh = 80%

Eh = 90%

Fh = 100%

21BRK_MODER/W0h Brake mode

0h = All three high side FETs turned ON

1h = All three low side FETs turned ON

20RESERVEDR/W0h Reserved
19-17RESERVEDR/W0h Reserved
16-13BRK_TIMER/W0h Brake time

0h = 10 ms

1h = 50 ms

2h = 100 ms

3h = 200 ms

4h = 300 ms

5h = 400 ms

6h = 500 ms

7h = 750 ms

8h = 1 s

9h = 2 s

Ah = 3 s

Bh = 4 s

Ch = 5 s

Dh = 7.5 s

Eh = 10 s

Fh = 15 s

12-9HIZ_TIMER/W0h Hi-Z time

0h = 10 ms

1h = 50 ms

2h = 100 ms

3h = 200 ms

4h = 300 ms

5h = 400 ms

6h = 500 ms

7h = 750 ms

8h = 1 s

9h = 2 s

Ah = 3 s

Bh = 4 s

Ch = 5 s

Dh = 7.5 s

Eh = 10 s

Fh = 15 s

8-6STAT_DETECT_THRR/W0h BEMF threshold to detect if motor is stationary

0h = 50 mV

1h = 75 mV

2h = 100 mV

3h = 250 mV

4h = 500 mV

5h = 750 mV

6h = 1000 mV

7h = 1500 mV

5-2REV_DRV_HANDOFF_THRR/W0h Speed threshold used to transition to open loop during reverse deceleration (% of MAX_SPEED)

0h = 2.5%

1h = 5%

2h = 7.5%

3h = 10%

4h = 12.5%

5h = 15%

6h = 20%

7h = 25%

8h = 30%

9h = 40%

Ah = 50%

Bh = 60%

Ch = 70%

Dh = 80%

Eh = 90%

Fh = 100%

1-0REV_DRV_OPEN_LOOP_CURRENTR/W0h Open loop current limit during speed reversal

0h = 1.5 A

1h = 2.5 A

2h = 3.5 A

3h = 5.0 A

7.7.1.2 REV_DRIVE_CONFIG Register (Address = 82h) [Reset = 00000000h]

REV_DRIVE_CONFIG is shown in REV_DRIVE_CONFIG Register and described in REV_DRIVE_CONFIG Register Field Descriptions.

Return to the Summary Table.

Register to configure reverse drive settings

Figure 7-56 REV_DRIVE_CONFIG Register
3130292827262524
PARITYREV_DRV_OPEN_LOOP_ACCEL_A1REV_DRV_OPEN_LOOP_ACCEL_A2
R/W-0hR/W-0hR/W-0h
2322212019181716
REV_DRV_OPEN_LOOP_ACCEL_A2ACTIVE_BRAKE_CURRENT_LIMITACTIVE_BRAKE_KP
R/W-0hR/W-0hR/W-0h
15141312111098
ACTIVE_BRAKE_KPACTIVE_BRAKE_KI
R/W-0hR/W-0h
76543210
ACTIVE_BRAKE_KI
R/W-0h
Table 7-16 REV_DRIVE_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-27REV_DRV_OPEN_LOOP_ACCEL_A1R/W0h Open loop acceleration coefficient A1 during reverse drive

0h = 0.01 Hz/s

1h = 0.05 Hz/s

2h = 1 Hz/s

3h = 2.5 Hz/s

4h = 5 Hz/s

5h = 10 Hz/s

6h = 25 Hz/s

7h = 50 Hz/s

8h = 75 Hz/s

9h = 100 Hz/s

Ah = 250 Hz/s

Bh = 500 Hz/s

Ch = 750 Hz/s

Dh = 1000 Hz/s

Eh = 5000 Hz/s

Fh = 10000 Hz/s

26-23REV_DRV_OPEN_LOOP_ACCEL_A2R/W0h Open loop acceleration coefficient A2 during reverse drive

0h = 0.0 Hz/s2

1h = 0.05 Hz/s2

2h = 1 Hz/s2

3h = 2.5 Hz/s2

4h = 5 Hz/s2

5h = 10 Hz/s2

6h = 25 Hz/s2

7h = 50 Hz/s2

8h = 75 Hz/s2

9h = 100 Hz/s2

Ah = 250 Hz/s2

Bh = 500 Hz/s2

Ch = 750 Hz/s2

Dh = 1000 Hz/s2

Eh = 5000 Hz/s2

Fh = 10000 Hz/s2

22-20ACTIVE_BRAKE_CURRENT_LIMITR/W0h Bus current limit during active braking

0h = 0.5 A

1h = 1 A

2h = 2 A

3h = 3 A

4h = 4 A

5h = 5 A

6h = 6 A

7h = 7 A

19-10ACTIVE_BRAKE_KPR/W0h 10-bit value for active braking loop Kp. Kp = ACTIVE_BRAKE_KP / 27
9-0ACTIVE_BRAKE_KIR/W0h 10-bit value for active braking loop Ki. Ki = ACTIVE_BRAKE_KI / 29

7.7.1.3 MOTOR_STARTUP1 Register (Address = 84h) [Reset = 00000000h]

MOTOR_STARTUP1 is shown in MOTOR_STARTUP1 Register and described in MOTOR_STARTUP1 Register Field Descriptions.

Return to the Summary Table.

Register to configure motor startup settings1

Figure 7-57 MOTOR_STARTUP1 Register
3130292827262524
PARITYMTR_STARTUPALIGN_SLOW_RAMP_RATEALIGN_TIME
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ALIGN_TIMEALIGN_OR_SLOW_CURRENT_ILIMITIPD_CLK_FREQ
R/W-0hR/W-0hR/W-0h
15141312111098
IPD_CLK_FREQIPD_CURR_THRIPD_RLS_MODE
R/W-0hR/W-0hR/W-0h
76543210
IPD_ADV_ANGLEIPD_REPEATOL_ILIMIT_CONFIGIQ_RAMP_ENACTIVE_BRAKE_ENREV_DRV_CONFIG
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-17 MOTOR_STARTUP1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-29MTR_STARTUPR/W0h Motor start-up method

0h = Align

1h = Double Align

2h = IPD

3h = Slow first cycle

28-25ALIGN_SLOW_RAMP_RATER/W0h Align, slow first cycle and open loop current ramp rate

0h = 0.1 A/s

1h = 1 A/s

2h = 5 A/s

3h = 10 A/s

4h = 15 A/s

5h = 25 A/s

6h = 50 A/s

7h = 100 A/s

8h = 150 A/s

9h = 200 A/s

Ah = 250 A/s

Bh = 500 A/s

Ch = 1000 A/s

Dh = 2000 A/s

Eh = 5000 A/s

Fh = No Limit A/s

24-21ALIGN_TIMER/W0h Align time

0h = 10 ms

1h = 50 ms

2h = 100 ms

3h = 200 ms

4h = 300 ms

5h = 400 ms

6h = 500 ms

7h = 750 ms

8h = 1 s

9h = 1.5 s

Ah = 2 s

Bh = 3 s

Ch = 4 s

Dh = 5 s

Eh = 7.5 s

Fh = 10 s

20-17ALIGN_OR_SLOW_CURRENT_ILIMITR/W0h Align or slow first cycle current limit

0h = 0.125 A

1h = 0.25 A

2h = 0.5 A

3h = 1.0 A

4h = 1.5 A

5h = 2.0 A

6h = 2.5 A

7h = 3.0 A

8h = 3.5 A

9h = 4.0 A

Ah = 4.5 A

Bh = 5.0 A

Ch = 5.5 A

Dh = 6.0 A

Eh = 7.0 A

Fh = 8.0 A

16-14IPD_CLK_FREQR/W0h IPD clock frequency

0h = 50 Hz

1h = 100 Hz

2h = 250 Hz

3h = 500 Hz

4h = 1000 Hz

5h = 2000 Hz

6h = 5000 Hz

7h = 10000 Hz

13-9IPD_CURR_THRR/W0h IPD current threshold

0h = 0.25 A

1h = 0.5 A

2h = 0.75 A

3h = 1.0 A

4h = 1.25 A

5h = 1.5 A

6h = 2.0 A

7h = 2.5 A

8h = 3.0 A

9h = 3.667 A

Ah = 4.0 A

Bh = 4.667 A

Ch = 5.0 A

Dh = 5.333 A

Eh = 6.0 A

Fh = 6.667 A

10h = 7.333 A

11h = 8.0 A

12h = NA

13h = NA

14h = NA

15h = NA

16h = NA

17h = NA

18h = NA

19h = NA

1Ah = NA

1Bh = NA

1Ch = NA

1Dh = NA

1Eh = NA

1Fh = NA

8IPD_RLS_MODER/W0h IPD release mode

0h = Brake

1h = Tristate

7-6IPD_ADV_ANGLER/W0h IPD advance angle

0h = 0°

1h = 30°

2h = 60°

3h = 90°

5-4IPD_REPEATR/W0h Number of times IPD is executed

0h = 1 time

1h = average of 2 times

2h = average of 3 times

3h = average of 4 times

3OL_ILIMIT_CONFIGR/W0h Open loop current limit configuration

0h = Open loop current limit defined by OL_ILIMIT

1h = Open loop current limit defined by ILIMIT

2IQ_RAMP_ENR/W0h Iq ramp down before transition to close loop

0h = Disable Iq ramp down

1h = Enable Iq ramp down

1ACTIVE_BRAKE_ENR/W0h Active braking enable

0h = Disable Active Brake

1h = Enable Active Brake

0REV_DRV_CONFIGR/W0h Chooses between forward and reverse drive setting for reverse drive

0h = Open loop current, A1, A2 based on forward drive

1h = Open loop current, A1, A2 based on reverse drive

7.7.1.4 MOTOR_STARTUP2 Register (Address = 86h) [Reset = 00000000h]

MOTOR_STARTUP2 is shown in MOTOR_STARTUP2 Register and described in MOTOR_STARTUP2 Register Field Descriptions.

Return to the Summary Table.

Register to configure motor startup settings2

Figure 7-58 MOTOR_STARTUP2 Register
3130292827262524
PARITYOL_ILIMITOL_ACC_A1
R/W-0hR/W-0hR/W-0h
2322212019181716
OL_ACC_A1OL_ACC_A2AUTO_HANDOFF_ENOPN_CL_HANDOFF_THR
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
OPN_CL_HANDOFF_THRALIGN_ANGLE
R/W-0hR/W-0h
76543210
SLOW_FIRST_CYC_FREQFIRST_CYCLE_FREQ_SELTHETA_ERROR_RAMP_RATE
R/W-0hR/W-0hR/W-0h
Table 7-18 MOTOR_STARTUP2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-27OL_ILIMITR/W0h Open loop current limit

0h = 0.125 A

1h = 0.25 A

2h = 0.5 A

3h = 1.0 A

4h = 1.5 A

5h = 2.0 A

6h = 2.5 A

7h = 3.0 A

8h = 3.5 A

9h = 4.0 A

Ah = 4.5 A

Bh = 5.0 A

Ch = 5.5 A

Dh = 6.0 A

Eh = 7.0 A

Fh = 8.0 A

26-23OL_ACC_A1R/W0h Open loop acceleration coefficient A1

0h = 0.01 Hz/s

1h = 0.05 Hz/s

2h = 1 Hz/s

3h = 2.5 Hz/s

4h = 5 Hz/s

5h = 10 Hz/s

6h = 25 Hz/s

7h = 50 Hz/s

8h = 75 Hz/s

9h = 100 Hz/s

Ah = 250 Hz/s

Bh = 500 Hz/s

Ch = 750 Hz/s

Dh = 1000 Hz/s

Eh = 5000 Hz/s

Fh = 10000 Hz/s

22-19OL_ACC_A2R/W0h Open loop acceleration coefficient A2

0h = 0.0 Hz/s2

1h = 0.05 Hz/s2

2h = 1 Hz/s2

3h = 2.5 Hz/s2

4h = 5 Hz/s2

5h = 10 Hz/s2

6h = 25 Hz/s2

7h = 50 Hz/s2

8h = 75 Hz/s2

9h = 100 Hz/s2

Ah = 250 Hz/s2

Bh = 500 Hz/s2

Ch = 750 Hz/s2

Dh = 1000 Hz/s2

Eh = 5000 Hz/s2

Fh = 10000 Hz/s2

18AUTO_HANDOFF_ENR/W0h Auto handoff enable

0h = Disable Auto Handoff (and use OPN_CL_HANDOFF_THR)

1h = Enable Auto Handoff

17-13OPN_CL_HANDOFF_THRR/W0h Open to close loop handoff threshold (% of MAX_SPEED)

0h = 1%

1h = 2%

2h = 3%

3h = 4%

4h = 5%

5h = 6%

6h = 7%

7h = 8%

8h = 9%

9h = 10%

Ah = 11%

Bh = 12%

Ch = 13%

Dh = 14%

Eh = 15%

Fh = 16%

10h = 17%

11h = 18%

12h = 19%

13h = 20%

14h = 22.5%

15h = 25%

16h = 27.5%

17h = 30%

18h = 32.5%

19h = 35%

1Ah = 37.5%

1Bh = 40%

1Ch = 42.5%

1Dh = 45%

1Eh = 47.5%

1Fh = 50%

12-8ALIGN_ANGLER/W0h Align angle

0h = 0°

1h = 10°

2h = 20°

3h = 30°

4h = 45°

5h = 60°

6h = 70°

7h = 80°

8h = 90°

9h = 110°

Ah = 120°

Bh = 135°

Ch = 150°

Dh = 160°

Eh = 170°

Fh = 180°

10h = 190°

11h = 210°

12h = 225°

13h = 240°

14h = 250°

15h = 260°

16h = 270°

17h = 280°

18h = 290°

19h = 315°

1Ah = 330°

1Bh = 340°

1Ch = 350°

1Dh = N/A

1Eh = N/A

1Fh = N/A

7-4SLOW_FIRST_CYC_FREQR/W0h Frequency of first cycle in close loop startup (% of MAX_SPEED)

0h = 1%

1h = 2%

2h = 3%

3h = 5%

4h = 7.5%

5h = 10%

6h = 12.5%

7h = 15%

8h = 17.5%

9h = 20%

Ah = 25%

Bh = 30%

Ch = 35%

Dh = 40%

Eh = 45%

Fh = 50%

3FIRST_CYCLE_FREQ_SELR/W0h First cycle frequency in open loop for align, double align and IPD startup options

0h = Defined by SLOW_FIRST_CYC_FREQ

1h = 0 Hz

2-0THETA_ERROR_RAMP_RATER/W0h Ramp rate for reducing difference between estimated theta and open loop theta

0h = 0.01 deg/ms

1h = 0.05 deg/ms

2h = 0.1 deg/ms

3h = 0.15 deg/ms

4h = 0.2 deg/ms

5h = 0.5 deg/ms

6h = 1 deg/ms

7h = 2 deg/ms

7.7.1.5 CLOSED_LOOP1 Register (Address = 88h) [Reset = 00000000h]

CLOSED_LOOP1 is shown in CLOSED_LOOP1 Register and described in CLOSED_LOOP1 Register Field Descriptions.

Return to the Summary Table.

Register to configure close loop settings1

Figure 7-59 CLOSED_LOOP1 Register
3130292827262524
PARITYOVERMODULATION_ENABLECL_ACCCL_DEC_CONFIG
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
CL_DECPWM_FREQ_OUT
R/W-0hR/W-0h
15141312111098
PWM_FREQ_OUTPWM_MODEFG_SELFG_DIV
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
FG_CONFIGFG_BEMF_THRAVS_ENDEADTIME_COMP_ENSPEED_LOOP_DISLOW_SPEED_RECIRC_BRAKE_EN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-19 CLOSED_LOOP1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30OVERMODULATION_ENABLER/W0h Overmodulation enable

0h = Disable Over Modulation

1h = Enable Over Modulation

29-25CL_ACCR/W0h Closed loop acceleration

0h = 0.5 Hz/s

1h = 1 Hz/s

2h = 2.5 Hz/s

3h = 5 Hz/s

4h = 7.5 Hz/s

5h = 10 Hz/s

6h = 20 Hz/s

7h = 40 Hz/s

8h = 60 Hz/s

9h = 80 Hz/s

Ah = 100 Hz/s

Bh = 200 Hz/s

Ch = 300 Hz/s

Dh = 400 Hz/s

Eh = 500 Hz/s

Fh = 600 Hz/s

10h = 700 Hz/s

11h = 800 Hz/s

12h = 900 Hz/s

13h = 1000 Hz/s

14h = 2000 Hz/s

15h = 4000 Hz/s

16h = 6000 Hz/s

17h = 8000 Hz/s

18h = 10000 Hz/s

19h = 20000 Hz/s

1Ah = 30000 Hz/s

1Bh = 40000 Hz/s

1Ch = 50000 Hz/s

1Dh = 60000 Hz/s

1Eh = 70000 Hz/s

1Fh = No limit

24CL_DEC_CONFIGR/W0h Closed loop deceleration configuration

0h = Closed loop deceleration defined by CL_DEC

1h = Closed loop deceleration defined by CL_ACC

23-19CL_DECR/W0h Closed loop deceleration. This register is used only if AVS is disabled and CL_DEC_CONFIG is set to '0'

0h = 0.5 Hz/s

1h = 1 Hz/s

2h = 2.5 Hz/s

3h = 5 Hz/s

4h = 7.5 Hz/s

5h = 10 Hz/s

6h = 20 Hz/s

7h = 40 Hz/s

8h = 60 Hz/s

9h = 80 Hz/s

Ah = 100 Hz/s

Bh = 200 Hz/s

Ch = 300 Hz/s

Dh = 400 Hz/s

Eh = 500 Hz/s

Fh = 600 Hz/s

10h = 700 Hz/s

11h = 800 Hz/s

12h = 900 Hz/s

13h = 1000 Hz/s

14h = 2000 Hz/s

15h = 4000 Hz/s

16h = 6000 Hz/s

17h = 8000 Hz/s

18h = 10000 Hz/s

19h = 20000 Hz/s

1Ah = 30000 Hz/s

1Bh = 40000 Hz/s

1Ch = 50000 Hz/s

1Dh = 60000 Hz/s

1Eh = 70000 Hz/s

1Fh = No limit

18-15PWM_FREQ_OUTR/W0h Output PWM switching frequency

0h = 10 kHz

1h = 15 kHz

2h = 20 kHz

3h = 25 kHz

4h = 30 kHz

5h = 35 kHz

6h = 40 kHz

7h = 45 kHz

8h = 50 kHz

9h = 55 kHz

Ah = 60 kHz

Bh = 65 kHz

Ch = 70 kHz

Dh = 75 kHz

Eh = N/A

Fh = N/A

14PWM_MODER/W0h PWM modulation

0h = Continuous Space Vector Modulation

1h = Discontinuous Space Vector Modulation

13-12FG_SELR/W0h FG select

0h = Output FG in open loop and closed loop

1h = Output FG in only closed loop

2h = Output FG in open loop for the first try.

3h = N/A

11-8FG_DIVR/W0h FG division factor

0h = Divide by 1 (2-pole motor mechanical speed)

1h = Divide by 1 (2-pole motor mechanical speed)

2h = Divide by 2 (4-pole motor mechanical speed)

3h = Divide by 3 (6-pole motor mechanical speed)

4h = Divide by 4 (8-pole motor mechanical speed) ...

Fh = Divide by 15 (30-pole motor mechanical speed)

7FG_CONFIGR/W0h FG output configuration

0h = FG active as long as motor is driven

1h = FG active till BEMF drops below BEMF threshold defined by FG_BEMF_THR

6-4FG_BEMF_THRR/W0h FG output BEMF threshold

0h = +/- 1mV

1h = +/- 2mV

2h = +/- 5mV

3h = +/- 10mV

4h = +/- 20mV

5h = +/- 30mV

6h = N/A

7h = N/A

3AVS_ENR/W0h AVS enable

0h = Disable

1h = Enable

2DEADTIME_COMP_ENR/W0h Deadtime compensation enable

0h = Disable

1h = Enable

1SPEED_LOOP_DISR/W0h Speed loop disable

0h = Enable

1h = Disable

0LOW_SPEED_RECIRC_BRAKE_ENR/W0h Stop mode applied when stop mode is recirculation brake and motor running in align or open loop

0h = Hi-z

1h = Low Side Brake

7.7.1.6 CLOSED_LOOP2 Register (Address = 8Ah) [Reset = 00000000h]

CLOSED_LOOP2 is shown in CLOSED_LOOP2 Register and described in CLOSED_LOOP2 Register Field Descriptions.

Return to the Summary Table.

Register to configure close loop settings2

Figure 7-60 CLOSED_LOOP2 Register
3130292827262524
PARITYMTR_STOPMTR_STOP_BRK_TIME
R/W-0hR/W-0hR/W-0h
2322212019181716
ACT_SPIN_THRBRAKE_SPEED_THRESHOLD
R/W-0hR/W-0h
15141312111098
MOTOR_RES
R/W-0h
76543210
MOTOR_IND
R/W-0h
Table 7-20 CLOSED_LOOP2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-28MTR_STOPR/W0h Motor stop method

0h = Hi-z

1h = Recirculation Mode

2h = Low side braking

3h = High side braking

4h = Active spin down

5h = Align braking

6h = N/A

7h = N/A

27-24MTR_STOP_BRK_TIMER/W0h Brake time during motor stop

0h = 0.1 ms

1h = 0.1 ms

2h = 0.25 ms

3h = 0.5 ms

4h = 1 ms

5h = 5 ms

6h = 10 ms

7h = 50 ms

8h = 100 ms

9h = 250 ms

Ah = 500 ms

Bh = 1000 ms

Ch = 2500 ms

Dh = 5000 ms

Eh = 10000 ms

Fh = 15000 ms

23-20ACT_SPIN_THRR/W0h Speed threshold for active spin down (% of MAX_SPEED)

0h = 100 %

1h = 90 %

2h = 80 %

3h = 70 %

4h = 60%

5h = 50 %

6h = 45 %

7h = 40 %

8h = 35 %

9h = 30 %

Ah = 25 %

Bh = 20 %

Ch = 15 %

Dh = 10 %

Eh = 5 %

Fh = 2.5 %

19-16BRAKE_SPEED_THRESHOLDR/W0h Speed threshold for BRAKE pin and motor stop options (low-side braking or high-side braking or align braking) (% of MAX_SPEED)

0h = 100 %

1h = 90 %

2h = 80 %

3h = 70 %

4h = 60%

5h = 50 %

6h = 45 %

7h = 40 %

8h = 35 %

9h = 30 %

Ah = 25 %

Bh = 20 %

Ch = 15 %

Dh = 10 %

Eh = 5 %

Fh = 2.5 %

15-8MOTOR_RESR/W0h 8-bit values for motor phase resistance
7-0MOTOR_INDR/W0h 8-bit values for motor phase inductance

7.7.1.7 CLOSED_LOOP3 Register (Address = 8Ch) [Reset = 00000000h]

CLOSED_LOOP3 is shown in CLOSED_LOOP3 Register and described in CLOSED_LOOP3 Register Field Descriptions.

Return to the Summary Table.

Register to configure close loop settings3

Figure 7-61 CLOSED_LOOP3 Register
3130292827262524
PARITYMOTOR_BEMF_CONST
R/W-0hR/W-0h
2322212019181716
MOTOR_BEMF_CONSTCURR_LOOP_KP
R/W-0hR/W-0h
15141312111098
CURR_LOOP_KPCURR_LOOP_KI
R/W-0hR/W-0h
76543210
CURR_LOOP_KISPD_LOOP_KP
R/W-0hR/W-0h
Table 7-21 CLOSED_LOOP3 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-23MOTOR_BEMF_CONSTR/W0h 8-bit values for motor BEMF constant
22-13CURR_LOOP_KPR/W0h 10-bit value for current Iq and Id loop Kp. Kp = 8LSB of CURR_LOOP_KP / 10^2MSB of CURR_LOOP_KP. Set to 0 for auto calculation of current loop Kp.
12-3CURR_LOOP_KIR/W0h 10-bit value for current Iq and Id loop Ki. Ki = 1000 * 8LSB of CURR_LOOP_KI / 10^2MSB of CURR_LOOP_KI. Set to 0 for auto calculation of current loop Ki.
2-0SPD_LOOP_KPR/W0h 3 MSB bits for speed loop Kp. Kp = 0.01 * 8LSB of SPD_LOOP_KP / 10^2MSB of SPD_LOOP_KP

7.7.1.8 CLOSED_LOOP4 Register (Address = 8Eh) [Reset = X]

CLOSED_LOOP4 is shown in CLOSED_LOOP4 Register and described in CLOSED_LOOP4 Register Field Descriptions.

Return to the Summary Table.

Register to configure close loop settings4

Figure 7-62 CLOSED_LOOP4 Register
3130292827262524
PARITYSPD_LOOP_KP
R/W-0hR/W-0h
2322212019181716
SPD_LOOP_KI
R/W-0h
15141312111098
SPD_LOOP_KIMAX_SPEED
R/W-0hR/W-X
76543210
MAX_SPEED
R/W-X
Table 7-22 CLOSED_LOOP4 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-24SPD_LOOP_KPR/W0h 7 LSB bits for speed loop Kp. Kp = 0.01 * 8LSB of SPD_LOOP_KP / 10^2MSB of SPD_LOOP_KP. Set to 0 for auto calculation of speed loop Kp.
23-14SPD_LOOP_KIR/W0h 10-bit value for speed loop Ki. Ki = 0.1 * 8LSB of SPD_LOOP_KI / 10^2MSB of SPD_LOOP_KI. Set to 0 for auto calculation of speed loop Ki.
13-0MAX_SPEEDR/WX 14-bit value for setting maximum value of speed in electrical Hz Maximum motor electrical speed (Hz): {MOTOR_SPEED/6} For example: if MOTOR_SPEED is 0x2710, then maximum motor speed (Hz) = 10000(0x2710)/6 = 1666 Hz

7.7.1.9 SPEED_PROFILES1 Register (Address = 94h) [Reset = X]

SPEED_PROFILES1 is shown in SPEED_PROFILES1 Register and described in SPEED_PROFILES1 Register Field Descriptions.

Return to the Summary Table.

Register to configure speed profile1

Figure 7-63 SPEED_PROFILES1 Register
3130292827262524
PARITYSPEED_PROFILE_CONFIGDUTY_ON1
R/W-0hR/W-0hR/W-X
2322212019181716
DUTY_ON1DUTY_OFF1
R/W-XR/W-X
15141312111098
DUTY_OFF1DUTY_CLAMP1
R/W-XR/W-X
76543210
DUTY_CLAMP1DUTY_A
R/W-XR/W-X
Table 7-23 SPEED_PROFILES1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-29SPEED_PROFILE_CONFIGR/W0h Configuration for speed profiles

0h = Speed Reference Mode

1h = Linear Mode

2h = Staircase Mode

3h = Forward Reverse Mode

28-21DUTY_ON1R/WX Duty_ON1 configuration (%) = {(DUTY_ON1/255)*100}
20-13DUTY_OFF1R/WX Duty_OFF1 Configuration (%) = {(DUTY_OFF1/255)*100}
12-5DUTY_CLAMP1R/WX Duty_CLAMP1 Configuration Duty Cycle for clamping speed (%) = {(DUTY_CLAMP1/255)*100}
4-0DUTY_AR/WX 5 MSB bits for Duty Cycle A

7.7.1.10 SPEED_PROFILES2 Register (Address = 96h) [Reset = X]

SPEED_PROFILES2 is shown in SPEED_PROFILES2 Register and described in SPEED_PROFILES2 Register Field Descriptions.

Return to the Summary Table.

Register to configure speed profile2

Figure 7-64 SPEED_PROFILES2 Register
3130292827262524
PARITYDUTY_ADUTY_B
R/W-0hR/W-XR/W-X
2322212019181716
DUTY_BDUTY_C
R/W-XR/W-X
15141312111098
DUTY_CDUTY_D
R/W-XR/W-X
76543210
DUTY_DDUTY_E
R/W-XR/W-0h
Table 7-24 SPEED_PROFILES2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-28DUTY_AR/WX 3 LSB bits for Duty Cycle A Duty_A Configuration Duty Cycle A (%) = {(DUTY_A/255)*100}
27-20DUTY_BR/WX Duty_B Configuration Duty Cycle B (%) = {(DUTY_B/255)*100}
19-12DUTY_CR/WX Duty_C Configuration Duty Cycle C (%) = {(DUTY_C/255)*100}
11-4DUTY_DR/WX Duty_D Configuration Duty Cycle D (%) = {(DUTY_D/255)*100}
3-0DUTY_ER/W0h 4 MSB bits for Duty Cycle E

7.7.1.11 SPEED_PROFILES3 Register (Address = 98h) [Reset = X]

SPEED_PROFILES3 is shown in SPEED_PROFILES3 Register and described in SPEED_PROFILES3 Register Field Descriptions.

Return to the Summary Table.

Register to configure speed profile3

Figure 7-65 SPEED_PROFILES3 Register
3130292827262524
PARITYDUTY_EDUTY_ON2
R/W-0hR/W-XR/W-X
2322212019181716
DUTY_ON2DUTY_OFF2
R/W-XR/W-X
15141312111098
DUTY_OFF2DUTY_CLAMP2
R/W-XR/W-X
76543210
DUTY_CLAMP2RESERVED
R/W-XR/W-0h
Table 7-25 SPEED_PROFILES3 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-27DUTY_ER/WX 4 LSB bits for Duty Cycle E Duty_E Configuration Duty Cycle E (%) = {(DUTY_E/255)*100}
26-19DUTY_ON2R/WX Duty_ON2 Configuration (%) = {(DUTY_ON2/255)*100}
18-11DUTY_OFF2R/WX Duty_OFF2 Configuration (%) = {(DUTY_OFF2/255)*100}
10-3DUTY_CLAMP2R/WX Duty_CLAMP2 Configuration Duty Cycle for clamping speed (%) = {(DUTY_CLAMP1/255)*100}
2-0RESERVEDR/W0h Reserved

7.7.1.12 SPEED_PROFILES4 Register (Address = 9Ah) [Reset = X]

SPEED_PROFILES4 is shown in SPEED_PROFILES4 Register and described in SPEED_PROFILES4 Register Field Descriptions.

Return to the Summary Table.

Register to configure speed profile4

Figure 7-66 SPEED_PROFILES4 Register
3130292827262524
PARITYSPEED_OFF1
R/W-0hR/W-X
2322212019181716
SPEED_OFF1SPEED_CLAMP1
R/W-XR/W-X
15141312111098
SPEED_CLAMP1SPEED_A
R/W-XR/W-X
76543210
SPEED_ASPEED_B
R/W-XR/W-X
Table 7-26 SPEED_PROFILES4 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-23SPEED_OFF1R/WX Turn off speed Configuration Turn off speed (% of MAX_SPEED) = {(SPEED_OFF1/255)*100}
22-15SPEED_CLAMP1R/WX Clamp Speed Configuration Clamp Speed (% of MAX_SPEED) = {(SPEED_CLAMP1/255)*100}
14-7SPEED_AR/WX Speed A configuration SPEED A (% of MAX_SPEED) = {(SPEED_A/255)*100}
6-0SPEED_BR/WX 7 MSB of SPEED_B configuration

7.7.1.13 SPEED_PROFILES5 Register (Address = 9Ch) [Reset = X]

SPEED_PROFILES5 is shown in SPEED_PROFILES5 Register and described in SPEED_PROFILES5 Register Field Descriptions.

Return to the Summary Table.

Register to configure speed profile5

Figure 7-67 SPEED_PROFILES5 Register
3130292827262524
PARITYSPEED_BSPEED_C
R/W-0hR/W-XR/W-X
2322212019181716
SPEED_CSPEED_D
R/W-XR/W-X
15141312111098
SPEED_DSPEED_E
R/W-XR/W-X
76543210
SPEED_ERESERVED
R/W-XR/W-0h
Table 7-27 SPEED_PROFILES5 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30SPEED_BR/WX 1 LSB of SPEED_B configuration Speed B Configuration SPEED B(% of MAX_SPEED) = {(SPEED_B/255)*100}
29-22SPEED_CR/WX Speed C configuration SPEED C (% of MAX_SPEED) = {(SPEED_A/255)*100}
21-14SPEED_DR/WX Speed D configuration SPEED D (% of MAX_SPEED) = {(SPEED_D/255)*100}
13-6SPEED_ER/WX Speed E Configuration SPEED E (% of MAX_SPEED) = {(SPEED_E/255)*100}
5-0RESERVEDR/W0h Reserved

7.7.1.14 SPEED_PROFILES6 Register (Address = 9Eh) [Reset = X]

SPEED_PROFILES6 is shown in SPEED_PROFILES6 Register and described in SPEED_PROFILES6 Register Field Descriptions.

Return to the Summary Table.

Register to configure speed profile6

Figure 7-68 SPEED_PROFILES6 Register
3130292827262524
PARITYSPEED_OFF2
R/W-0hR/W-X
2322212019181716
SPEED_OFF2SPEED_CLAMP2
R/W-XR/W-X
15141312111098
SPEED_CLAMP2RESERVED
R/W-XR/W-X
76543210
RESERVED
R/W-X
Table 7-28 SPEED_PROFILES6 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-23SPEED_OFF2R/WX Turn off speed Configuration Turn off speed (% of MAX_SPEED) = {(SPEED_OFF2/255)*100}
22-15SPEED_CLAMP2R/WX Clamp Speed Configuration Clamp Speed (% of MAX_SPEED) = {(SPEED_CLAMP2/255)*100}
14-0RESERVEDR/WX Reserved