ZHCSK16A October 2017 – July 2019 LMK04228
PRODUCTION DATA.
Digital (coarse) delay allows a group of outputs to be delayed by 4 to 32 VCO cycles. The delay step can be as small as half the period of the VCO cycle by using the DCLKoutX_HS bit. It is fixed digital delay.
The regular clock divider is substituted with an alternative divide value. The substitute divide value consists of two values, DCLKoutX_DDLY_CNTH and DCLKoutX_DDLY_CNTL. The minimum _CNTH/_CNTL value is 2 and the maximum _CNTH/_CNTL value is 16. This will result in a minimum alternative divide value of 4 and a maximum of 32.