ZHCSK16A October 2017 – July 2019 LMK04228
PRODUCTION DATA.
This register has controls for enabling clock in switch events.
BIT | NAME | POR DEFAULT | DESCRIPTION | |
---|---|---|---|---|
7 | NA | 0 | Reserved | |
6 | CLKin
_OVERRIDE |
0 | When CLKin_SEL_MODE = 0/1/2 to select a manual clock input, CLKin_OVERRIDE = 1 will force that clock input. Used with clock distribution mode for best performance.
0: Normal, no override. 1: Force select of only CLKin0/1/2 as specified by CLKin_SEL_MODE in manual mode. |
|
5 | NA | 0 | Reserved | |
4 | HOLDOVER
_PLL1_DET |
0 | This enables the HOLDOVER when PLL1 lock detect signal transitions from high to low.
0: PLL1 DLD does not cause a clock switch event 1: PLL1 DLD causes a clock switch event |
|
3 | HOLDOVER
_LOS_DET |
0 | This enables HOLDOVER when PLL1 LOS signal is detected.
0: Disabled 1: Enabled |
|
2 | HOLDOVER
_VTUNE_DET |
0 | Enables the DAC Vtune rail detections. When the DAC achieves a specified Vtune, if this bit is enabled, the current clock input is considered invalid and an input clock switch event is generated.
0: Disabled 1: Enabled |
|
1 | HOLDOVER
_HITLESS _SWITCH |
1 | Determines whether a clock switch event will enter holdover use hitless switching.
0: Hard Switch 1: Hitless switching (has an undefined switch time) |
|
0 | HOLDOVER_EN | 1 | Sets whether holdover mode is active or not.
0: Disabled 1: Enabled |