ZHCSKF4C March 2017 – October 2019 LMH1228
PRODUCTION DATA.
The LMH1228 default loop bandwidth setting is optimized for a wide variety of applications. For applications using the Intel Arria 10 FPGA, further optimization of the loop bandwidth may be required. Refer to the LMH1228 and LMH1208 Programming Guide (SNAU206) for detailed register settings when using the LMH1228 with an Arria 10 FPGA.