ZHCSUG9 January   2024 LMG3100R017

ADVANCE INFORMATION  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
  7. 6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay and Mismatch Measurement
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Control Inputs
      2. 8.3.2 Start-up and UVLO
      3. 8.3.3 Bootstrap Supply Voltage Clamping
      4. 8.3.4 Level Shift
    4. 8.4 Device Functional Modes
  10.   Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 VCC Bypass Capacitor
        2. 9.2.2.2 Bootstrap Capacitor
        3. 9.2.2.3 Slew Rate Control
        4. 9.2.2.4 Use With Analog Controllers
        5. 9.2.2.5 Power Dissipation
    3.     Power Supply Recommendations
    4. 9.3 Layout
      1. 9.3.1 Layout Guidelines
      2. 9.3.2 Layout Examples
  11. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Information
    2. 11.2 Tape and Reel Information

封装选项

机械数据 (封装 | 引脚)
  • VBE|15
散热焊盘机械数据 (封装 | 引脚)
订购信息

5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
ICC VCC Quiescent Current LI = HI = 0V, VCC = 5V 0.08 0.125 mA
ICC VCC Quiescent Current LI=VCC=5V, HI=0V 0.17 5 mA
ICCO Total VCC Operating Current f = 500 kHz, 50% Duty cycle, VIN = 48V  10 15.0 mA
IHB HB Quiescent Current LI = HI = 0V, VCC = 5V, HB-HS = 4.6V 0.1 0.150 mA
IHB HB Quiescent Current LI=0V, HI=VCC=5V, HB-HS=4.6V, VIN=48V 0.16 0.25 mA
INPUT PINS
VIH High-Level Input Voltage Threshold Rising Edge 1.87 2.06 2.22 V
VIL Low-Level Input Voltage Threshold Falling Edge 1.48 1.66 1.76 V
VHYS Hysteresis between rising and falling threshold 350 mV
RI Input pull down resistance 100 200 300 kΩ
OUTPUT PINS
VOL Low level output voltage IOL = 10 mA 0.01 V
VOH High level output voltage IOL = -10 mA VHB-0.03 V
UNDER VOLTAGE PROTECTION
VCCR VCC Rising edge threshold Rising 3.2 3.8 4.5 V
VCCF VCC Falling edge threshold 3.0 3.6 4.3 V
VCC(hyst) VCC UVLO threshold hysteresis 217 mV
VHBR HB Rising edge threshold Rising 2.5 3.2 3.9 V
VHBF HB Falling edge threshold 2.3 3.0 3.7 V
VHB(hyst) HB UVLO threshold hysteresis 224 mV
BOOTSTRAP DIODE
VDL Low-Current forward voltage IVDD-HB = 100µA 0.45 0.65 V
VDH High current forward voltage IVDD-HB = 100mA 0.9 1.0 V
RD Dynamic Resistance IVDD-HB = 100mA 1.85 Ω
HB-HS Clamp Regulation Voltage 4.65 5 5.2 V
tBS Bootstrap diode reverse recovery time IF = 100 mA, IR = 100 mA 40 ns
QRR Bootstrap diode reverse recovery charge VVIN = 50 V 2 nC
POWER STAGE R017
RDS(ON) GaN FET on-resistance LI=VCC=5V, HI=0V, I(DRN-SRC)=30A, TJ = 25℃ 1.7 2.2 mΩ
VSD GaN 3rd quadrant conduction drop ISD = 500 mA, VVCC = 5 V, HI = LI = 0V 1.5 V
IL-DRN-SRC Leakage from DRN to SRC when the GaN FET is off DRN = 80V, HI = LI = 0V, VVCC = 5V, TJ=25℃ 12 300 µA
COSS Output Capacitance of GaN FET VDS=50V, VGS= 0V (HI = LI = 0V) 880 980 pF
COSS(ER) Output Capacitance of GaN FET - Energy Related VDS=0 to 50V, VGS= 0V (HI = LI = 0V) 1058 pF
COSS(TR) Output Capacitance of GaN FET - Time Related VDS=0 to 50V, VGS= 0V (HI = LI = 0V) 1422 pF
QG Total Gate Charge of high side or low side HEMT VDS=50V, ID= 30A, VGS= 5V 20.3 29 nC
QGD Gate to Drain Charge of high side or low side HEMT VDS=50V, ID= 16A 1.8 nC
QGS Gate to Source Charge of high side or low side HEMT VDS=50V, ID= 16A 6 nC
QOSS Output Charge  VDS=50V, ID= 16A 76 88 nC
QRR Source to Drain Reverse Recovery Charge Not including internal driver bootstrap diode 0 nC
tHIPLH Propagation delay: HI Rising(2) LI=0V, VCC=5V, HB-HS=5V, VIN=48V 55 90 ns
tHIPHL Propagation delay: HI Falling(2) LI=0V, VCC=5V, HB-HS=5V, VIN=48V 55 90 ns
tLPLH Propagation delay: LI Rising(2) HI=0V, VCC=5V, HB-HS=5V, VIN=48V 29.5 50 ns
tLPHL Propagation delay: LI Falling(2) HI=0V, VCC=5V, HB-HS=5V, VIN=48V 29.5 50 ns
tMON Delay Matching: LI high & HI low(2) 25 40 ns
tMOFF Delay Matching: LI low & HI high(2) 25 40 ns
tPW Minimum Input Pulse Width that Changes the Output 10 ns
(1) Parameters that show only a typical value are determined by design and may not be tested in production
(2) See Propagation Delay and Mismatch Measurement section