ZHCS547K January   2010  – February 2018 LM27402

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      典型应用电路
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Performance Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Wide Input Voltage Range
      2. 7.3.2  UVLO
      3. 7.3.3  Precision Enable
      4. 7.3.4  Soft-Start and Voltage Tracking
      5. 7.3.5  Output Voltage Setpoint and Accuracy
      6. 7.3.6  Voltage-Mode Control
      7. 7.3.7  Power Good
      8. 7.3.8  Inductor-DCR-Based Overcurrent Protection
      9. 7.3.9  Current Sensing
      10. 7.3.10 Power MOSFET Gate Drivers
      11. 7.3.11 Pre-Bias Start-up
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fault Conditions
        1. 7.4.1.1 Thermal Protection
        2. 7.4.1.2 Current Limit
        3. 7.4.1.3 Negative Current Limit
        4. 7.4.1.4 Undervoltage Threshold (UVT)
        5. 7.4.1.5 Overvoltage Threshold (OVT)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Converter Design
      2. 8.1.2  Inductor Selection (L)
      3. 8.1.3  Output Capacitor Selection (COUT)
      4. 8.1.4  Input Capacitor Selection (CIN)
      5. 8.1.5  Using Precision Enable
      6. 8.1.6  Setting the Soft-Start Time
      7. 8.1.7  Tracking
      8. 8.1.8  Setting the Switching Frequency
      9. 8.1.9  Setting the Current Limit Threshold
      10. 8.1.10 Control Loop Compensation
      11. 8.1.11 MOSFET Gate Drivers
      12. 8.1.12 Power Loss and Efficiency Calculations
        1. 8.1.12.1 Power MOSFETs
        2. 8.1.12.2 High-Side Power MOSFET
        3. 8.1.12.3 Low-Side Power MOSFET
        4. 8.1.12.4 Gate-Charge Loss
        5. 8.1.12.5 Input and Output Capacitor ESR Losses
        6. 8.1.12.6 Inductor Losses
        7. 8.1.12.7 Controller Losses
        8. 8.1.12.8 Overall Efficiency
    2. 8.2 Typical Applications
      1. 8.2.1 Example Circuit 1
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Example Circuit 2
      3. 8.2.3 Example Circuit 3
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Stage Layout
      2. 10.1.2 Gate Drive Layout
      3. 10.1.3 Controller Layout
      4. 10.1.4 Thermal Design and Layout
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 第三方产品免责声明
      2. 11.1.2 开发支持
        1. 11.1.2.1 使用 WEBENCH® 工具创建定制设计
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Electrical Characteristics

Unless otherwise stated, the following conditions apply: VVIN = 12 V. Limits in standard type are for TJ = 25°C only. Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C and are provided for reference purposes only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATIONAL SPECIFICATIONS
IQ Quiescent Current VFB = 0.6 V (not switching), TJ = 25°C 4.5 mA
VFB = 0.6 V (not switching), TJ = –40°C to +125°C 6
IQSD Quiescent Current In Shutdown VEN = 0 V, TJ = 25°C 25 µA
VEN = 0 V, TJ = –40°C to +125°C 45
UVLO
UVLO Input Under Voltage Lockout VVIN Rising, VVDD Rising, TJ = 25°C 2.9 V
VVIN Rising, VVDD Rising, TJ = –40°C to +125°C 2.7 2.99
UVLOHYS UVLO Hysteresis VVIN Falling, VVDD Falling 300 mV
REFERENCE
VFB Feedback Voltage TJ = 25°C 0.600 V
TJ = –40°C to +125°C 0.594 0.606
IFB Feedback Pin Bias Current VFB = 0.65 V –50 0 50 nA
SWITCHING
FSW Switching Frequency RFADJ = 4.12 kΩ, TJ = 25°C 1150 kHz
RFADJ = 4.12 kΩ, TJ = –40°C to +125°C 950 1350
RFADJ = 20 kΩ, TJ = 25°C 500 kHz
RFADJ = 4.12 kΩ, TJ = –40°C to +125°C 400 0 600
RFADJ = 95.3 kΩ, TJ = 25°C 214 kHz
RFADJ = 4.12 kΩ, TJ = –40°C to +125°C 175 265
DMAX Maximum Duty Cycle FSW = 300 kHz, TJ = 25°C 95%
FSW = 300 kHz, TJ = –40°C to +125°C 93%
VDD SUB-REGULATOR
VDD Sub-Regulator Output Voltage IDD = 25 mA, TJ = 25°C 4.5 V
IDD = 25 mA, TJ = –40°C to +125°C 4 5
ERROR AMPLIFIER
BW–3dB Open Loop Bandwidth 2 MHz
AVOL Error Amp DC Gain 50 dB
VSLEW_RISE Error Amplifier Rising Slew Rate VFB = 0.5 V 5 V/µs
VSLEW_FALL Error Amplifier Falling Slew Rate VFB = 0.7 V 3 V/µs
ISOURCE COMP Source Current VFB = 0.5 V 8 12 mA
ISINK COMP Sink Current VFB = 0.7 V 4 12 mA
VCOMP_MAX Max COMP Voltage VFB = 0.5 V 3.1 V
VCOMP_MIN Min COMP Voltage VFB = 0.7 V 0.5 V
OVER CURRENT
VOFFSET Comparator Voltage Offset TJ = 25°C 0 mV
TJ = –40°C to +125°C –5 5
ICS– Current Limit Offset Current VCS– = 5 V, TJ = 25°C 10 µA
VCS– = 5 V, TJ = –40°C to +125°C 9.5 10.5
GATE DRIVE
RDSON1 High-Side FET Driver pullup On Resistance VCBOOT – VSW = 4.7 V, IHG = +100 mA 1.7 Ω
RDSON2 High-Side FET Driver pulldown On Resistance VCBOOT – VSW = 4.7 V, IHG = –100 mA 1.2 Ω
RDSON3 Low-Side FET Driver pullup On Resistance VVDD = 4.7 V, ILG = +100 mA 1.7 Ω
RDSON4 Low-Side FET Driver pulldown On Resistance VVDD = 4.7 V, ILG = –100 mA 1 Ω
SOFT-START
ISS Soft-Start Source Current VSS/TRACK = 0 V, TJ = 25°C 3 µA
VSS/TRACK = 0 V, TJ = –40°C to +125°C 2 4
RSS_PD Soft-Start pulldown Resistance VSS/TRACK = 0.6 V 288 Ω
POWERGOOD
IPGS PGOOD Low Sink Current VPGOOD = 0.2 V, VFB = 0.75 V, TJ = 25°C 60 µA
VPGOOD = 0.2 V, VFB = 0.75 V, TJ = –40°C to +125°C 0 100
IPGL PGOOD Leakage Current VPGOOD = 5 V 1 10 µA
OVT Overvoltage Threshold VFB Rising, TJ = 25°C 117%
VFB Rising, TJ = –40°C to +125°C 114% 120%
OVT_HYS OVT Hysteresis VFB Falling 2%
UVT Undervoltage Threshold VFB Rising , TJ = 25°C 94%
VFB Rising, TJ = –40°C to +125°C 91% 97%
UVT_HYS UVT Hysteresis VFB Falling 3%
ENABLE
VEN Enable Logic High Threshold VEN Rising, TJ = 25°C 1.17 V
VEN Rising, TJ = –40°C to +125°C 1.10 1.24
VEN_HYS Enable Hysteresis VEN Falling 100 mV
IEN Enable Pin pullup Current VEN = 0 V 2 µA
FREQUENCY SYNCHRONIZATION
VLH_SYNC SYNC Pin Logic High VVDD = 4.7 V, TJ = –40°C to +125°C 2.0 V
VLL_SYNC SYNC Pin Logic Low VVDD = 4.7 V, TJ = –40°C to +125°C 0.8 V
SYNCFSW_L Minimum Clock Sync Frequency TJ = –40°C to +125°C 200 kHz
SYNCFSW_H Maximum Clock Sync Frequency TJ = –40°C to +125°C 1200 kHz
THERMAL SHUTDOWN
TSHD Thermal Shutdown Temperature Rising 165 °C
TSHD_HYS Thermal Shutdown Hysteresis Temperature Falling 15 °C