ZHCSH27B May   2017  – April 2018 IWR1642

PRODUCTION DATA.  

  1. 1 器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能框图
  2. 2 修订历史记录
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
      1. Table 4-3 PAD IO Register Bit Descriptions
    3. 4.3 Signal Descriptions
      1. Table 4-4 Signal Descriptions - Digital
      2. Table 4-5 Signal Descriptions - Analog
    4. 4.4 Pin Multiplexing
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Supply Specifications
    6. 5.6  Power Consumption Summary
    7. 5.7  RF Specification
    8. 5.8  CPU Specifications
    9. 5.9  Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    10. 5.10 Timing and Switching Characteristics
      1. 5.10.1  Power Supply Sequencing and Reset Timing
      2. 5.10.2  Input Clocks and Oscillators
        1. 5.10.2.1 Clock Specifications
      3. 5.10.3  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 5.10.3.1 Peripheral Description
        2. 5.10.3.2 MibSPI Transmit and Receive RAM Organization
          1. Table 5-7   SPI Timing Conditions
          2. Table 5-8   SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. Table 5-9   SPI Master Mode Input Timing Requirements (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          4. Table 5-10 SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          5. Table 5-11 SPI Master Mode Input Requirements (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
        3. 5.10.3.3 SPI Slave Mode I/O Timings
          1. Table 5-12 SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
          2. Table 5-13 SPI Slave Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        4. 5.10.3.4 Typical Interface Protocol Diagram (Slave Mode)
      4. 5.10.4  LVDS Interface Configuration
        1. 5.10.4.1 LVDS Interface Timings
      5. 5.10.5  General-Purpose Input/Output
        1. Table 5-15 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      6. 5.10.6  Controller Area Network Interface (DCAN)
        1. Table 5-16 Dynamic Characteristics for the DCANx TX and RX Pins
      7. 5.10.7  Serial Communication Interface (SCI)
        1. Table 5-17 SCI Timing Requirements
      8. 5.10.8  Inter-Integrated Circuit Interface (I2C)
        1. Table 5-18 I2C Timing Requirements
      9. 5.10.9  Quad Serial Peripheral Interface (QSPI)
        1. Table 5-19 QSPI Timing Conditions
        2. Table 5-20 Timing Requirements for QSPI Input (Read) Timings
        3. Table 5-21 QSPI Switching Characteristics
      10. 5.10.10 ETM Trace Interface
        1. Table 5-22 ETMTRACE Timing Conditions
        2. Table 5-23 ETM TRACE Switching Characteristics
      11. 5.10.11 Data Modification Module (DMM)
        1. Table 5-24 DMM Timing Requirements
      12. 5.10.12 JTAG Interface
        1. Table 5-25 JTAG Timing Conditions
        2. Table 5-26 Timing Requirements for IEEE 1149.1 JTAG
        3. Table 5-27 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  6. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Subsystems
      1. 6.3.1 RF and Analog Subsystem
        1. 6.3.1.1 Clock Subsystem
        2. 6.3.1.2 Transmit Subsystem
        3. 6.3.1.3 Receive Subsystem
      2. 6.3.2 Processor Subsystem
      3. 6.3.3 Host Interface
      4. 6.3.4 Master Subsystem Cortex-R4F Memory Map
      5. 6.3.5 DSP Subsystem Memory Map
    4. 6.4 Other Subsystems
      1. 6.4.1 ADC Channels (Service) for User Application
        1. Table 6-3 GP-ADC Parameter
  7. 7 Monitoring and Diagnostics
    1. 7.1 Monitoring and Diagnostic Mechanisms
      1. 7.1.1 Error Signaling Module
  8. 8 Applications, Implementation, and Layout
    1. 8.1 Application Information
    2. 8.2 Reference Schematic
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
      3. 8.3.3 Stackup Details
  9. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Community Resources
    5. 9.5 商标
    6. 9.6 静电放电警告
    7. 9.7 出口管制提示
    8. 9.8 术语表
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information

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6.3.5 DSP Subsystem Memory Map

Table 6-2 shows the DSP C674x memory map.

Table 6-2 DSP C674x Memory Map

Name Frame Address (Hex) Size Description
Start End
DSP Memories
DSP_L1D 0x00F0_0000 0x00F0_7FFF 32 KiB L1 data memory space
DSP_L1P 0x00E0_0000 0x00E0_7FFF 32 KiB L1 program memory space
DSP_L2_UMAP0 0x0080_0000 0x0081_FFFF 128 KiB L2 RAM space
DSP_L2_UMAP1 0x007E_0000 0x007F_FFFF 128 KiB L2 RAM space
EDMA
TPCC0 0x0201_0000 0x0201_3FFF 16 KiB TPCC0 module configuration space
TPCC1 0x020A_0000 0x020A_3FFF 16 KiB TPCC1 module configuration space
TPTC0 0x0200 0000 0x0200 03FF 1 KiB TPTC0 module configuration space
TPTC1 0x0200 0800 0x0200 0BFF 1 KiB TPTC1 module configuration space
TPTC2 0x0209_0000 0x0209_03FF 1 KiB TPTC2 module configuration space
TPTC3 0x0209_0400 0x0209_07FF 1 KiB TPTC3 module configuration space
Control Registers
DSS_REG 0x0200_0400 0x0200_07FF 864 B DSPSS control module registers
DSS_REG2 0x0200_0C00 0x0200_0FFF 624 B DSPSS control module registers
System Memories
ADC Buffer 0x2100_0000 0x2100_7FFC 32 KiB ADC buffer memory space
CBUFF-FIFO 0x2102_0000 0x2102_3FFC 16 KiB Common buffer FIFO space
L3-Shared memory 0x2000_0000 0x201F_FFFF 2 MB(1) L3 shared memory space
HS-RAM 0x2108_0000 0x2108_7FFC 32 KiB Handshake memory space
System Peripherals
RTI-A/WD 0x0202_0000 0x0202_00FF 192 B RTI-A module configuration registers
RTI-B 0x020F_0000 0x020F_00FF 192 B RTI-B module configuration registers
CBUFF 0x0207_0000 0x0207_03FF 564 B Common Buffer module Configuration registers
Mail Box
MSS<->RADARSS		 0x5060_1000 0x5060_17FF 2 KiB RADARSS to MSS mailbox memory space
0x5060_2000 0x5060_27FF MSS to RADARSS mailbox memory space
0x0460_8000 0x0460_80FF 188 B MSS to RADARSS mailbox Configuration registers
0x0460_8060 0x0460_86FF RADARSS to MSS mailbox Configuration registers
Mail Box
MSS<->DSPSS		 0x5060_4000 0x5060_47FF 2 KiB DSPSS to MSS mailbox memory space
0x5060_5000 0x5060_57FF MSS to DSPSS mailbox memory space
0x0460_8400 0x0460_84FF 188 B MSS to DSPSS mailbox Configuration registers
0x0460_8300 0x0460_83FF DSPSS to MSS mailbox Configuration registers
Mail Box
RADARSS<->DSPSS		 0x5060_6000 0x5060_67FF 2 KiB RADARSS to DSPSS mailbox memory space
0x5060_7000 0x5060_7FFF DSPSS to RADARSS mailbox memory space
0x0460_8200 0x0460_82FF 188 B RADARSS to DSPSS mailbox Configuration registers
0x0460_8100 0x0460_81FF DSPSS to RADARSS mailbox Configuration registers
Safety Modules
ESM 0x020D_0000 92 B ESM module Configuration registers
CRC 0x2200_0000 0x2200_03FF 1 KiB CRC module Configuration registers
STC 0x0204_0000 0x0204_01FF 284 B STC module Configuration registers
Nonsystem Peripherals
SCI 0x0203_0000 0x0203_00FF 148 B SCI module Configuration registers
(1) 768 KB memory within 2 MB memory space