ZHCSLL4 December   2021 DP83TC814R-Q1 , DP83TC814S-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Diagnostic Tool Kit
        1. 8.3.1.1 Signal Quality Indicator
        2. 8.3.1.2 Electrostatic Discharge Sensing
        3. 8.3.1.3 Time Domain Reflectometry
        4. 8.3.1.4 Voltage Sensing
        5. 8.3.1.5 BIST and Loopback Modes
          1. 8.3.1.5.1 Data Generator and Checker
          2. 8.3.1.5.2 xMII Loopback
          3. 8.3.1.5.3 PCS Loopback
          4. 8.3.1.5.4 Digital Loopback
          5. 8.3.1.5.5 Analog Loopback
          6. 8.3.1.5.6 Reverse Loopback
      2. 8.3.2 Compliance Test Modes
        1. 8.3.2.1 Test Mode 1
        2. 8.3.2.2 Test Mode 2
        3. 8.3.2.3 Test Mode 4
        4. 8.3.2.4 Test Mode 5
    4. 8.4 Device Functional Modes
      1. 8.4.1  Power Down
      2. 8.4.2  Reset
      3. 8.4.3  Standby
      4. 8.4.4  Normal
      5. 8.4.5  Media Dependent Interface
        1. 8.4.5.1 100BASE-T1 Master and 100BASE-T1 Slave Configuration
        2. 8.4.5.2 Auto-Polarity Detection and Correction
        3. 8.4.5.3 Jabber Detection
        4. 8.4.5.4 Interleave Detection
      6. 8.4.6  MAC Interfaces
        1. 8.4.6.1 Media Independent Interface
        2. 8.4.6.2 Reduced Media Independent Interface
        3. 8.4.6.3 Reduced Gigabit Media Independent Interface
      7. 8.4.7  Serial Management Interface
      8. 8.4.8  Direct Register Access
      9. 8.4.9  Extended Register Space Access
      10. 8.4.10 Write Address Operation
        1. 8.4.10.1 MMD1 - Write Address Operation
      11. 8.4.11 Read Address Operation
        1. 8.4.11.1 MMD1 - Read Address Operation
      12. 8.4.12 Write Operation (No Post Increment)
        1. 8.4.12.1 MMD1 - Write Operation (No Post Increment)
      13. 8.4.13 Read Operation (No Post Increment)
        1. 8.4.13.1 MMD1 - Read Operation (No Post Increment)
      14. 8.4.14 Write Operation (Post Increment)
        1. 8.4.14.1 MMD1 - Write Operation (Post Increment)
      15. 8.4.15 Read Operation (Post Increment)
        1. 8.4.15.1 MMD1 - Read Operation (Post Increment)
    5. 8.5 Programming
      1. 8.5.1 Strap Configuration
      2. 8.5.2 LED Configuration
      3. 8.5.3 PHY Address Configuration
    6. 8.6 Register Maps
      1. 8.6.1 Register Access Summary
      2. 8.6.2 DP83TC814 Registers
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Physical Medium Attachment
          1. 9.2.1.1.1 Common-Mode Choke Recommendations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Signal Traces
      2. 11.1.2 Return Path
      3. 11.1.3 Metal Pour
      4. 11.1.4 PCB Layer Stacking
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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订购信息

Pin Configuration and Functions

Figure 6-1 DP83TC814S-Q1 RHA Package
36-Pin VQFN
Top View
Figure 6-2 DP83TC814R-Q1 RHA Package
36-Pin VQFN
Top View
Table 6-1 Pin Functions
PIN STATE1 DESCRIPTION
NAME2 NO.
MAC INTERFACE

RX_D3
RX_M

23 S, PD, O

Receive Data: Symbols received on the cable are decoded and transmitted out of these pins synchronous to the rising edge of RX_CLK. They contain valid data when RX_DV is asserted. A data nibble, RX_D[3:0], is transmitted in MII and RGMII modes. 2 bits; RX_D[1:0], are transmitted in RMII mode. RX_D[3:2] are not used when in RMII mode.

If the PHY is bootstrapped to RMII Master mode, a 50-MHz clock reference is automatically outputted on RX_D3. This clock must be fed to the MAC.

RX_M / RX_P: Differential SGMII Data Output. These pins transmit data from the PHY to the MAC.

RX_D2
RX_P

24

RX_D1

25

RX_D0

26
RX_CLK 27 PD, O

Receive Clock: In MII and RGMII modes, the receive clock provides a 25-MHz reference clock.

Unused in RMII and SGMII modes

RX_ER 14 S, PD, O

Receive Error: In MII and RMII modes, this pin indicates a receive error symbol has been detected within a received packet. In MII mode, RX_ER is asserted high synchronously to the rising edge of RX_CLK. In RMII mode, RX_ER is asserted high synchronously to the rising edge of the reference clock. This pin is not required to be used by the MAC in MII or RMII because the PHY will automatically corrupt data on a receive error.

Unused in RGMII and SGMII modes

RX_DV
CRS_DV
RX_CTRL
15 S, PD, O

Receive Data Valid: This pin indicates when valid data is presented on RX_D[3:0] for MII mode.

Carrier Sense Data Valid: This pin combines carrier sense and data valid into an asynchronous signal. When CRS_DV is asserted, data is presented on RX_D[1:0] in RMII mode.

RGMII Receive Control: Receive control combines receive data valid indication and receive error indication into a single signal. RX_DV is presented on the rising edge of RX_CLK and RX_ER is presented on the falling edge of RX_CLK.

Unused in SGMII mode

TX_CLK 28 PD, I, O

Transmit Clock: In MII mode, the transmit clock is a 25-MHz output and has constant phase referenced to the reference clock. In RGMII mode, this clock is sourced from the MAC layer to the PHY. A 25-MHz clock must be provided (not required to have constant phase to the reference clock unless synchronous RGMII is enabled)

Unused in RMII and SGMII modes

TX_EN
TX_CTRL
29 PD, I

Transmit Enable: In MII mode, transmit enable is presented prior to the rising edge of the transmit clock. TX_EN indicates the presence of valid data inputs on TX_D[3:0]. In RMII mode, transmit enable is presented prior to the rising edge of the reference clock. TX_EN indicates the presence of valid data inputs on TX_D[1:0].

RGMII Transmit Control: Transmit control combines transmit enable and transmit error indication into a single signal. TX_EN is presented prior to the rising edge of TX_CLK; TX_ER is presented prior to the falling edge of TX_CLK.

Unused in SGMII mode

TX_D3 30 PD, I

Transmit Data: In MII and RGMII modes, the transmit data nibble, TX_D[3:0], is received from the MAC prior to the rising edge of TX_CLK. In RMII mode, TX_D[1:0] is received from the MAC prior to the rising edge of the reference clock. TX_D[3:2] are not used in RMII mode.

TX_M / TX_P: Differential SGMII Data Input. These pins receive data that is transmitted from the MAC to the PHY.

TX_D2 31

TX_D1
TX_P

32

TX_D0
TX_M

33
SERIAL MANAGEMENT INTERFACE
MDC 1 I

Management Data Clock: Synchronous clock to the MDIO serial management input and output data. This clock may be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 25 MHz. There is no minimum clock rate.

MDIO 36 OD, IO

Management Data Input/Output: Bidirectional management data signal that may be sourced by the management station or the PHY. This pin requires a pullup resistor. In systems with multiple PHYs using same MDIO-MDC bus, a single pull-up resistor should be used on MDIO line.

Recommended to use a resistor between 2.2 kΩ and 9 kΩ.

CONTROL INTERFACE
INT 2 PU, OD, IO

Interrupt: Active-LOW output, which will be asserted LOW when an interrupt condition occurs. This pin has a weak internal pullup. Register access is necessary to enable various interrupt triggers. Once an interrupt event flag is set, register access is required to clear the interrupt event. This pin can be configured as an Active-HIGH output using register 0x0011.

This pin can also operate as Power-Down control where asserting this pin low would put the PHY in power down mode and asserting high would put the PHY in normal mode. This feature can also be enabled via register 0x0011.

RESET 3 PU, I

Reset: Active-LOW input, which initializes or reinitializes the PHY. Asserting this pin LOW for at least 1 μs will force a reset process to occur. All internal registers will reinitialize to their default states as specified for each bit in the Register Maps section. All bootstrap pins are resampled upon deassertion of reset.

CLOCK INTERFACE
XI 5 I

Reference Clock Input (RMII): Reference clock 50-MHz CMOS-level oscillator in RMII Slave mode. Reference clock 25-MHz crystal or oscillator in RMII Master mode.

Reference Clock Input (Other MAC Interfaces): Reference clock 25-MHz crystal or oscillator input. The device supports either an external crystal resonator connected across pins XI and XO, or an external CMOS-level oscillator connected to pin XI only and XO left floating. This pin can also accept clock input from other devices like Ethernet MAC or another Ethernet PHY in daisy-chain operations.

XO 4 O

Reference Clock Output: XO pin is used for crystal only. This pin must be left floating when a CMOS-level oscillator is connected to XI.

LED/GPIO INTERFACE
LED_0 / GPIO_0 35 S, PD, IO

LED_0: Link Status LED. This pin can also be used as LED or clock output via Register selection.

LED_1 / GPIO_1 6 S, PD, IO

LED_1: Link Status and BLINK for TX/RX Activity. This pin can also be used as LED or clock output via Strap/Register selection.

CLKOUT / GPIO_2 16 IO

Clock Output: 25-MHz reference clock. This pin can also be used as LED or GPIO via Strap/Register selection.

MEDIUM DEPENDENT INTERFACE
TRD_M 13 IO

Differential Transmit and Receive: Bidirectional differential signaling configured for 100BASE-T1 operation, IEEE 802.3bw compliant.

TRD_P 12
GROUND ESCAPE
GND_ESC 17

Ground Escape: Optional ground escape pins. These pins can be connected to ground to optimize PCB layout. These pins are not substitute for power ground connection to DAP. DAP must always be connected to power ground.

This pin can be left unconnected if not used.

GND_ESC 18

Ground Escape: Optional ground escape pins. These pins can be connected to ground to optimize PCB layout. These pins are not substitute for power ground connection to DAP. DAP must always be connected to power ground.

This pin can be left unconnected if not used.

POWER CONNECTIONS
VDDA 11 SUPPLY

Core Supply: 3.3 V

Recommend using 0.47-µF and 0.01-µF ceramic decoupling capacitors; optional ferrite bead can be used.

VDDIO 34 SUPPLY

IO Supply: 1.8 V, 2.5 V, or 3.3 V

Recommend using ferrite bead, 0.47-µF and 0.01-µF ceramic decoupling capacitors.

VDDMAC 22 SUPPLY

Optional MAC Interface Supply: 1.8 V, 2.5 V, or 3.3 V

Optional separate supply for MAC interface pins. This pin supplies power to the MAC interface pins and can be kept at a different voltage level as compared to other IO pins. Recommend using 0.47-µF, and 0.01-µF ceramic decoupling capacitors and ferrite bead. When separate VDDMAC is not required in the system then it must be connected to VDDIO. When connecting to VDDIO, 0.47-µF on the VDDIO can be removed. 0.47-µF must still be connected close to VDDMAC. In this case, one common ferrite bead can be used between VDDIO and VDDMAC.

VDDA 7 SUPPLY

VDDA Supply: 3.3 V

Recommend using 0.1-µF ceramic decoupling capacitors.

GROUND DAP GROUND

Ground: This must always be connected to power ground.

DO NOT CONNECT
DNC 8

DNC: Do not connect (leave floating)

DNC 10

DNC: Do not connect (leave floating)

DNC 19

DNC: Do not connect (leave floating)

DNC 20

DNC: Do not connect (leave floating)

NO CONNECT
NC 9

NC: No connection. Can be left floating. Connecting to any signal will have no effect on PHY performance.

NC 21

NC: No connection. Can be left floating. Connecting to any signal will have no effect on PHY performance.

  1. Pin Type:
    I = Input
    O = Output
    IO = Input/Output
    OD = Open Drain
    PD = Internal pulldown
    PU = Internal pullup
    S = Bootstrap configuration pin (all configuration pins have weak internal pullups or pulldowns)
  2. When pins are unused, follow the recommended connection requirements provided in the table above. If pins do not have required termination, they may be left floating.
Table 6-2 Pin Domain
PIN NO PIN NAME VOLTAGE DOMAIN
1 MDC VDDIO
2 INT_N VDDIO
3 RESET_N VDDIO
4 XO VDDIO
5 XI VDDIO
6 LED_1/GPIO_1 VDDIO
12 TRD_P VDDA
13 TRD_M VDDA
14 RX_ER VDDMAC
15 RX_DV/CRS_DV/RX_CTRL VDDMAC
16 CLKOUT/GPIO_2 VDDMAC
23 RX_D3/RX_M VDDMAC
24 RX_D2/RX_P VDDMAC
25 RX_D1 VDDMAC
26 RX_D0 VDDMAC
27 RX_CLK VDDMAC
28 TX_CLK VDDMAC
29 TX_EN/TX_CTRL VDDMAC
30 TX_D3 VDDMAC
31 TX_D2 VDDMAC
32 TX_D1/TX_P VDDMAC
33 TX_D0/TX_M VDDMAC
35 LED_0/GPIO_0 VDDIO
36 MDIO VDDIO
Table 6-3 Pin States - POWER-UP / RESET
PIN NO PIN
NAME
POWER-UP / RESET
PIN STATE (1) PULL TYPE PULL VALUE
(kΩ)
1 MDC I none none
2 INT I PU 9
3 RESET I PU 9
4 XO O none none
5 XI I none none
6 LED_1 I PD 9
7

VDDA

SUPPLY none none
8

DNC

I/O PD 455
9 NC FLOAT none none
10

DNC

OD, O none none
11 VDDA SUPPLY none none
12 TRD_P IO none none
13 TRD_M IO none none
14 RX_ER I PD 6
15 RX_DV I PD 6
16 CLKOUT O none none
17 GND_ESC FLOAT none none
18 GND_ESC I PD 50
19 DNC FLOAT none none
20 DNC FLOAT none none
21 NC FLOAT none none
22 VDDMAC SUPPLY none none
23 RX_D3 I PD 9
24 RX_D2 I PD 9
25 RX_D1 I PD 9
26 RX_D0 I PD 9
27 RX_CLK I PD 9
28 TX_CLK I none none
29 TX_EN I none none
30 TX_D3 I none none
31 TX_D2 I none none
32 TX_D1 I none none
33 TX_D0 I none none
34 VDDIO SUPPLY none none
35 LED_0 I PD 9
36 MDIO OD, IO none none
Table 6-4 Pin States - MAC ISOLATE and IEEE PWDN
PIN NO PIN
NAME
MAC ISOLATE IEEE PWDN
PIN STATE (1) PULL TYPE PULL VALUE
(kΩ)
PIN STATE (1) PULL TYPE PULL VALUE
(kΩ)
1 MDC I none none I none none
2 INT OD, O PU 9 OD, O PU 9
3 RESET I PU 9 I PU 9
4 XO O none none O none none
5 XI I none none I none none
6 LED_1 O none none O none none
7

VDDA

SUPPLY none none SUPPLY none none
8

DNC

IO PD 455 IO PD 455
9 NC FLOAT none none FLOAT none none
10

DNC

OD, O none none OD, O none none
11 VDDA SUPPLY none none SUPPLY none none
12 TRD_P IO none none IO none none
13 TRD_M IO none none IO none none
14 RX_ER I PD 6 I PD 6
15 RX_DV I PD 6 O none none
16 CLKOUT O none none O none none
17 GND_ESC FLOAT none none FLOAT none none
18 GND_ESC FLOAT none none FLOAT none none
19 DNC FLOAT none none FLOAT none none
20 DNC FLOAT none none FLOAT none none
21 DNC FLOAT none none FLOAT none none
22 VDDMAC SUPPLY none none SUPPLY none none
23 RX_D3 I PD 9 O none none
24 RX_D2 I PD 9 O none none
25 RX_D1 I PD 9 O none none
26 RX_D0 I PD 9 O none none
27 RX_CLK I PD 9 O none none
28 TX_CLK I PD 9 I none none
29 TX_EN I PD 9 I none none
30 TX_D3 I PD 9 I none none
31 TX_D2 I PD 9 I none none
32 TX_D1 I PD 9 I none none
33 TX_D0 I PD 9 I none none
34 VDDIO SUPPLY none none SUPPLY none none
35 LED_0 O none none O none none
36 MDIO OD, IO none none OD, IO none none
Table 6-5 Pin States - MII and RGMII
PIN NO PIN
NAME
MII RGMII
PIN STATE (1) PULL TYPE PULL VALUE
(kΩ)
PIN STATE (1) PULL TYPE PULL VALUE
(kΩ)
1 MDC I none none I none none
2 INT OD, O PU 9 OD, O PU 9
3 RESET I PU 9 I PU 9
4 XO O none none O none none
5 XI I none none I none none
6 LED_1 O none none O none none
7

VDDA

SUPPLY none none SUPPLY none none
8

DNC

IO PD 455 IO PD 455
9 NC FLOAT none none FLOAT none none
10

DNC

OD, O none none OD, O none none
11 VDDA SUPPLY none none SUPPLY none none
12 TRD_P IO none none IO none none
13 TRD_M IO none none IO none none
14 RX_ER O none none I PD 6
15 RX_DV O none none O none none
16 CLKOUT O none none O none none
17 GND_ESC FLOAT none none FLOAT none none
18 GND_ESC FLOAT none none FLOAT none none
19 DNC FLOAT none none FLOAT none none
20 DNC FLOAT none none FLOAT none none
21 DNC FLOAT none none FLOAT none none
22 VDDMAC SUPPLY none none SUPPLY none none
23 RX_D3 O none none O none none
24 RX_D2 O none none O none none
25 RX_D1 O none none O none none
26 RX_D0 O none none O none none
27 RX_CLK O none none O none none
28 TX_CLK O none none I none none
29 TX_EN I none none I none none
30 TX_D3 I none none I none none
31 TX_D2 I none none I none none
32 TX_D1 I none none I none none
33 TX_D0 I none none I none none
34 VDDIO SUPPLY none none SUPPLY none none
35 LED_0 O none none O none none
36 MDIO OD, IO none none OD, IO none none
Table 6-6 Pin States - RMII MASTER and RMII SLAVE
PIN NO PIN
NAME
RMII MASTER RMII SLAVE
PIN STATE (1) PULL TYPE PULL VALUE
(kΩ)
PIN STATE (1) PULL TYPE PULL VALUE
(kΩ)
1 MDC I none none I none none
2 INT OD, O PU 9 OD, O PU 9
3 RESET I PU 9 I PU 9
4 XO O none none O none none
5 XI I none none I none none
6 LED_1 O none none O none none
7

VDDA

SUPPLY none none SUPPLY none none
8

DNC

IO PD 455 IO PD 455
9 NC FLOAT none none FLOAT none none
10

DNC

OD, O none none OD, O none none
11 VDDA SUPPLY none none SUPPLY none none
12 TRD_P IO none none IO none none
13 TRD_M IO none none IO none none
14 RX_ER O none none O none none
15 RX_DV O none none O none none
16 CLKOUT O none none O none none
17 GND_ESC FLOAT none none FLOAT none none
18 GND_ESC FLOAT none none FLOAT none none
19 DNC FLOAT none none FLOAT none none
20 DNC FLOAT none none FLOAT none none
21 DNC FLOAT none none FLOAT none none
22 VDDMAC SUPPLY none none SUPPLY none none
23 RX_D3 O, 50MHz none none I PD 9
24 RX_D2 I PD 9 I PD 9
25 RX_D1 O none none O none none
26 RX_D0 O none none O none none
27 RX_CLK I PD 9 I PD 9
28 TX_CLK I none none I none none
29 TX_EN I none none I none none
30 TX_D3 I none none I none none
31 TX_D2 I none none I none none
32 TX_D1 I none none I none none
33 TX_D0 I none none I none none
34 VDDIO SUPPLY none none SUPPLY none none
35 LED_0 O none none O none none
36 MDIO OD, IO none none OD, IO none none
Table 6-7 Pin States - SGMII
PIN NO PIN
NAME
SGMII
PIN STATE (1) PULL TYPE PULL VALUE
(kΩ)
1 MDC I none none
2 INT OD, O PU 9
3 RESET I PU 9
4 XO O none none
5 XI I none none
6 LED_1 O none none
7

VDDA

SUPPLY none none
8

DNC

IO PD 455
9 NC FLOAT none none
10

DNC

OD, O none none
11 VDDA SUPPLY none none
12 TRD_P IO none none
13 TRD_M IO none none
14 RX_ER I PD 6
15 RX_DV I PD 6
16 CLKOUT O none none
17 GND_ESC FLOAT none none
18 GND_ESC FLOAT none none
19 DNC FLOAT none none
20 DNC FLOAT none none
21 DNC FLOAT none none
22 VDDMAC SUPPLY none none
23 RX_D3 O none none
24 RX_D2 O none none
25 RX_D1 I PD 9
26 RX_D0 I PD 9
27 RX_CLK I PD 9
28 TX_CLK I none none
29 TX_EN I none none
30 TX_D3 I none none
31 TX_D2 I none none
32 TX_D1 I none none
33 TX_D0 I none none
34 VDDIO SUPPLY none none
35 LED_0 O none none
36 MDIO OD, IO none none
Type: I = Input
O = Output
IO = Input/Output
OD = Open Drain
PD = Internal pulldown
PU = Internal pullup