ZHCSDE3G February 2015 – October 2022 DP83867CR , DP83867IR
PRODUCTION DATA
请参考 PDF 数据表获取器件具体的封装图。
BIT | BIT NAME | DEFAULT | DESCRIPTION |
---|---|---|---|
15:0 | LOOP_CFG_VAL | 1110 0111 0010 0001, RW | Loopback Configuration Value: 1110 0111 0010 000: Configuration for loopback modes. A software reset through bit 14 of the Control Register (CTRL), address 0x001F, is required after changes to this register value. Other values for this register are not recommended. |