DLPS292A July   2025  – December 2025 DLPC8424 , DLPC8444 , DLPC8454

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Compatability Table
  6. 5 Pin Configuration and Functions
    1.     7
    2. 5.1  Initialization, Board Level Test, and Debug
    3. 5.2  V-by-One Interface Input Data and Control
    4. 5.3  FPD-Link Port(s) Input Data and Control
    5. 5.4  DSI Input Data and Clock (Not Supported in DLPC8424, DLPC8444, and DLPC8454)
    6. 5.5  DMD SubLVDS Interface
    7. 5.6  DMD Reset and Low Speed Interfaces
    8. 5.7  Flash Interface
    9. 5.8  Peripheral Interfaces
    10. 5.9  GPIO Peripheral Interface
    11. 5.10 Clock and PLL Support
    12. 5.11 Power and Ground
    13. 5.12 I/O Type Subscript Definition
    14. 5.13 Internal Pullup and Pulldown Characteristics
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2.     23
    3. 6.2  ESD Ratings
    4. 6.3  Recommended Operating Conditions
    5. 6.4  Thermal Information
    6. 6.5  Power Electrical Characteristics
    7. 6.6  Pin Electrical Characteristics
    8. 6.7  DMD SubLVDS Interface Electrical Characteristics
    9.     30
    10. 6.8  DMD Low Speed Interface Electrical Characteristics
    11.     32
    12. 6.9  V-by-One Interface Electrical Characteristics
    13. 6.10 FPD Link LVDS Electrical Characteristics
    14. 6.11 USB Electrical Characteristics
    15.     36
    16. 6.12 System Oscillator Timing Requirements
    17.     38
    18. 6.13 Power Supply and Reset Timing Requirements
    19.     40
    20. 6.14 V-by-One Interface General Timing Requirements
    21.     42
    22. 6.15 FPD Link Interface General Timing Requirements
    23. 6.16 Flash Interface Timing Requirements
    24.     45
    25. 6.17 Source Frame Timing Requirements
    26.     47
    27. 6.18 Synchronous Serial Port Interface Timing Requirements
    28.     49
    29. 6.19 I2C Interface Timing Requirements
    30. 6.20 Programmable Output Clock Timing Requirements
    31. 6.21 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    32.     53
    33. 6.22 DMD Low Speed Interface Timing Requirements
    34.     55
    35. 6.23 DMD SubLVDS Interface Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Input Sources
      2. 7.3.2 V-by-One Interface
      3. 7.3.3 FPD-Link Interface
      4. 7.3.4 DMD (SubLVDS) Interface
      5. 7.3.5 Serial Flash Interface
      6. 7.3.6 GPIO Supported Functionality
        1.       67
        2.       68
      7. 7.3.7 Debug Support
  9. 8 Power Supply Recommendations
    1. 8.1 System Power-Up and Power-Down Sequence
    2. 8.2 DMD Fast Park Control (PARKZ)
    3. 8.3 Power Supply Management
    4. 8.4 Hotplug Usage
    5. 8.5 Power Supplies for Unused Input Source Interfaces
    6. 8.6 Power Supplies
      1. 8.6.1 Power Supplies DLPA3085 or DLPA3082
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Layout Guideline for DLPC8424 or DLPC8444 or DLPC8454 Reference Clock
        1. 9.1.1.1 Recommended Crystal Oscillator Configuration
      2. 9.1.2 V-by-One Interface Layout Considerations
      3. 9.1.3 DMD Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
      4. 9.1.4 Power Supply Layout Guidelines
    2. 9.2 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Device Nomenclature
      1. 10.5.1 Device Markings
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
      1. 10.8.1 Video Timing Parameter Definitions
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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5.11 Power and Ground

PIN I/O (1) DESCRIPTION
NAME NO.
VDDA18_PLLM AL11 PWR 1.8V (Nominal) for the Main I/F PLL
VDDA18_PLLD J13 PWR 1.8V (Nominal) for the DMD I/F PLL
VDD_CORE AA13, AA15, AA21, AB16, AC13, AD6, AD8, AD18, AD20, AE9, AE11, AF14, AF16, AF20, AG7, AH6, AJ11, AL9, AL13, AL17, AL19, K8, K18, L9, L13, M6, M20, N15, N17, T6, T12, T14, T20, U19, V8, V10, Y6, Y20 PWR
VDDAR_CORE AB10, AB12, AJ9, AJ13, AJ15, AJ17, AJ19, AK8, N11, N13, P8, P18, R9, R19, W15, W17 PWR
VDDA_CORE_DSI AR7 PWR
VDDA_CORE_FPD AM16, AM18, AM20 PWR 0.8V (Nominal) Fixed Power for FPD core
VDDA_CORE_USB AM6 PWR 0.8V (Nominal) for USB Controller
VDDA_CORE_Vx1 AM10, AM14 PWR 0.8V (Nominal) Fixed Power for Vx1 core
VDDA18_DDI J7, J9, J11, J15, J17, J19 PWR 1.8V (Nominal) Fixed IO Power for SubLVDS DMD Interface
VDDA18_DSI AP8 PWR 1.8V (Nominal) for DSI
VDDA18_FPD AN15, AP16, AP18, AR19 PWR 1.8V (Nominal) Fixed Power for FPD I/O
VDDA18_USB AN7 PWR 1.8V (Nominal) for USB Phy
VDDA18_Vx1 AM12, AP10, AP14 PWR 1.8V (Nominal) Fixed Power for Vx1 I/O
VDDA33_USB AP6 PWR 3.3V (Nominal) for USB Phy
VDDS18_LVCMOS1 AA5, AE5, AG5, AL5, W5
VDDS18_LVCMOS2 N21, R21, U21, W21
VDDS18_OSC U5 PWR 1.8V (Nominal) Fixed Power for Reference Oscillator I/O
VDDSHV_FLSH AC21, AE21 PWR 1.8V or 3.3V (Nominal) Multi-Voltage IO Power for the Quad-Serial Flash Interface
VDDSHV_INTF AG21, AL21 PWR 1.8V or 3.3V (Nominal) Multi-Voltage IO Power for SPI and I2C I/O (including GPIO[8:0]) to support the PAD1000 in place of a PMIC I/O. Also HOST_IRQ.
VSS A1, A9, A23, A25, AA7, AA9, AA17, AA19, AB6, AB8, AB14, AB18, AB20, AC5, AC9, AC11, AC15, AC17, AD12, AD14, AD16, AE13, AE17, AF6, AF8, AF12, AF18, AG9, AG11, AG13, AG17, AG19, AH10, AH14, AH16, AH20, AK6, AK16, AK20, AL7, AL15, AM8, AN5, AN9, AN21, AP12, AP20, AR5, AR9, AR11, AR13, AR15, AR17, AR21, AT4, AT6, AT8, AT10, AT12, AT14, AT18, AT22, AU3, AU7, AU23, AV2, AV10, AV14, AW7, AW19, AY2, AY14, AY24, B16, BA1, BA7, BA19, BA25, BB2, BB14, BB24, C9, C23, D2, D16, G5, G7, G9, G11, G15, G17, G19, G21, H6, H8, H10, H12, H14, H16, H18, H20, J5, J21, K6, K10, K16, K20, L5, L7, L11, L15, L17, M2, M10, M14, M18    , N5, N7, P10, P12, P14, P20, R5, R11, R15, R17, T8, T10, T16, U7, U11, U15, U17, V6, V12, V14, V20, W7, W13, W19, Y8, Y10, Y12, Y14, Y18   RTN Ground, at package level all grounds tie to VSS
VPP L21 RTN Manufacturing use only (efuse). Must be tied to ground.
(1) See Section 5.12 for more information on I/O definitions.