ZHCSA85F August 2012 – February 2019 DLPC410
RST_ACTIVE is an output from the DLPC410 to indicate to the user that a user requested Reset (MCP) has been accepted by the DLPC410. Shortly after the user requests a Reset (MCP) by asserting the appropriate Block Control signals defined in DMD Block Control Signals, RST_ACTIVE output to the user will transition to logic '1' for approximately 4.5 µs indicating a Mirror Clocking Pulse operation is in progress. While RST_ACTIVE is logic '1', no additional Mirror Clocking Pulse requests may be initiated by the user until RST_ACTIVE returns to logic '0'. RST_ACTIVE is synchronized to a version of DCLKIN. As such, circuits in the application FPGA should consider this signal asynchronous and use standard synchronization techniques to assure reliable registering of this signal.
After a Mirror Clocking Pulse or Clear command is given, RST_ACTIVE may not be asserted until up to 60ns after the command. During this time, no other command should be given.