ZHCSA85F August   2012  – February 2019 DLPC410


  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      简化应用
  4. 修订历史记录
  5. 说明 (续)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Electrical Characteristics
    5. 7.5 Timing Requirements
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 DLPC410 Binary Pattern Data Path
        1.  DIN_A, DIN_B, DIN_C, DIN_D Input Data Buses
        2.  DCLKIN Input Clocks
        3.  DVALID Input Signals
        4.  DOUT_A, DOUT_B, DOUT_C, DOUT_D Output Data Buses
        5.  DCLKOUT Output Clocks
        6.  SCTRL Output Signals
        7.  Supported DMD Bus Sizes
        8.  Row Cycle definition
        9.  DLP9500 and DLP9500UV Input Data Formatting
        10. DLP7000 and DLP7000UV Input Data Bus
        11. DLP650LNIR Input Data Bus
      2. 8.3.2 Data Bus Operations
        1. Row Addressing
        2. Single Row Write Operation
        3. No-Op Row Cycle Description
      3. 8.3.3 DMD Block Operations
        1. Mirror Clocking Pulse (MCP)
        2. Reset Active (RST_ACTIVE)
        3. DMD Block Control Signals
          1. Block Mode - BLK_MD1:0)
          2. Block Address - BLK_AD(3:0)
          3. Reset 2 Blocks - RST2BLK
        4. DMD Block Operations
          1. Global Reset (MCP) Consideration
      4. 8.3.4 Other Data Control Inputs
        1. Complement Data
        2. North/South Flip
      5. 8.3.5 Miscellaneous Control Inputs
        1. ARST
        2. CLKIN_R
        3. DMD_A_RESET
        4. Watchdog Timer Enable (WDT_ENABLE)
      6. 8.3.6 Miscellaneous Status Outputs
        1. INIT_ACTIVE
        2. DMD_Type(3:0)
        3. DDC_VERSION(3:0)
        4. LED0
        5. LED1
        6. DLPA200 Control Signals
        7. ECM2M_TP_ (31:0)
    4. 8.4 Device Functional Modes
      1. 8.4.1 DLPC410 Initialization and Training
        1. Initialization
        2. input Data Interface (DIN) Training Pattern
      2. 8.4.2 DLPC410 Operational Modes
        1. Single Block Mode
        2. Single Block Phased Mode
        3. Dual Block Mode
        4. Quad Block Mode
        5. Global Mode
        6. DMD Park Mode
        7. DMD Idle Mode
      3. 8.4.3 LOAD4 Functionality (enabled with DLPR410A)
        1. Enabling LOAD4
        2. Loading Data with LOAD4
        3. Row Mapping with LOAD4
        4. Using Block Clear with LOAD4
        5. Timing Requirements for LOAD4
        6. Global Binary Pattern Rate increases using LOAD4
        7. Special LOAD4 considerations
    5. 8.5 Programming
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Description
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Setup
      1. 9.3.1 Debugging Guidelines
      2. 9.3.2 Initialization
        1. Calibration
        2. DLPA200 Number 1 Initialization
        3. DMD Initialization
          1. DMD Device ID Check
          2. DMD Device OK
        4. DLPA200 Number 2 Initialization
        5. Command Sequence Initialization
      3. 9.3.3 Image Display Issues
        1. Present Data to DLPC410
        2. Load Data to DMD
        3. Mirror Clocking Pulse
  10. 10Power Supply Recommendations
    1. 10.1 Power Down Operation
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Impedance Requirements
      2. 11.1.2 PCB Signal Routing
      3. 11.1.3 Fiducials
      4. 11.1.4 PCB Layout Guidelines
        1. DMD Interface
          1. Trace Length Matching
        2. DLPC410 DMD Decoupling
          1. Decoupling Capacitors
        3. VCC and VCC2
        4. DMD Layout
        5. DLPA200
    2. 11.2 Layout Example
    3. 11.3 DLPC410 Chipset Connections
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 器件标记
      2. 12.1.2 器件命名规则
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13机械、封装和可订购信息


机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)


The DLPC410 DMD Digital Controller enables customers to stream binary pattern data to the DLP650LNIR, DLP7000(UV), or DLP9500(UV) DMD for very high speed binary pattern imaging applications. The DLPC410 receives customer input binary pattern data on a row by row basis and passes the pattern data to the connected DMD. Concurrent with the receipt of data, the DLPC410 captures the customer requested ROW mode and ROW address which determines if row loading starts at the top (or bottom) of the DMD and increments (or decrements) to the next row for the next Row Cycle, or if a specific row address is specified for loading the next pattern data. Each DMD micromirror is individually configurable through this data loading process which enables precise, predictable control of each and every micromirror in the DMD Micromirror array.

The DLPC410 also receives customer input control information instructing the DLPC410 to command the DLPA200 device(s) to generate the Mirror Clocking Pulses (MCPs) to the DMD – these MCPs are necessary for the DMD micromirrors to transition from their current state to their new state, the new state being determined by the new data just loaded into the DMD. A feedback signal from the DLPC410 frames the MCP such that the customer knows the MCP request has been received by the DLPC410 and when the MCP is completed.

The DLPC410 supports multiple MCP modes of operation. The DMD Micromirror arrays are arranged into horizontal Reset Blocks – there are typically 16 horizontal Reset Blocks per DMD where each Reset Block receives a single MCP to initiate the Micromirror state change. DMD blocks can be Reset one at a time or all at once. In certain modes, adjacent blocks of 2 or of 4 Reset Blocks can be Reset at the same time. This flexibility provides great advantages to optimizing the time certain DMD blocks are in certain states, which in turn can provide speed advantages or extend DMD illumination windows (the duration for which a solid state illuminator should be illuminating).

Behind the scenes, the DLPC410 also communicates directly with the control logic of the DMD to read part type and status information and to configure the DMD for proper operation. The DLPC410 is always paired with the DLPR410 PROM as the DLPR410 provides the configuration bit stream which configures the DLPC410 to be a DMD Digital Controller. The DLPC410 also drives one DMD at a time, and that DMD could require either one or two DLPA200 devices depending on the DMD type. For further information, refer to Table 11 or the individual DMD datasheets (links can be found in Table 26).