ZHCSA85F August 2012 – February 2019 DLPC410
Previous sections have described in detail how to send binary pattern data through the DLPC410 Controller to the connected DMD. Although the data loading process involves loading the specified data into the SRAM cells in the DMD array, this loading of data does not change the physical state of the DMD Micromirrors. The state of the mirrors can only be changed (or left the same if the data under the mirrors is unchanged) when a Mirror Clocking Pulse (Reset) is applied to the DMD MBRST pins from the DLPA200.
A sequence of Mirror Clocking Pulses (Resets) begins by asserting a row cycle with BLK_MD and BLK_AD as described in Table 14. Shortly after the row cycle, RST_ACTIVE output to the customer transitions to logic '1' for approximately 4.5 µs indicating a Mirror Clocking Pulse operation is in progress. During this time, no additional Mirror Clocking Pulses may be initiated until RST_ACTIVE returns to logic '0'.
RST_ACTIVE does not return to logic '0' unless: