ZHCSA85F August 2012 – February 2019 DLPC410
DCLKIN is the differential input clock for each DLPC410 input data bus. There are four input clocks, one for each bus (A/B/C/D). DCLKIN is a 400 MHz clock to the DMD which should be synchronous and edge aligned with all data and control signals for that specific bus (A, B, C, or D). Depending on the design, skewing the clock to data relationship may cause a problem. For timing constraints for the input data clock to either the input data and/or DVALID, refer to Timing Requirements. Care should be take to keep clock jitter of these signals to a minimum.