ZHCSA85F August 2012 – February 2019 DLPC410
The DLPC410, having captured the incoming pattern data on its input data buses, provides this data on an equivalent number of output data buses. The DLPC410 has four differential 16-bit output data buses (A/B/C/D), which are aligned to its input data buses. Which of these input data bus signals are used at any given time is specific to the DMD connected to the DLPC410 in the system. The data buses are 2xLVDS double-data-rate (DDR) buses which can transfer data at 800 MHz data rates per output. Data should be synchronous and edge aligned with the output clocks for each specific data bus (A, B, C, or D). Depending on the design, skewing the clock to data relationship may cause a problem. For timing constraints for the output data clock to the output data, refer to Timing Requirements.