ZHCSA85F August 2012 – February 2019 DLPC410
Once initialization is complete (INIT_ACTIVE = 0) the user is free to send data and control information to the DLPC410. When the user asserts the DVALID signal for the LVDS input buses, the DLPC410 samples the customer supplied binary input pattern data (DIN) as well as the Row Mode, Row Address, Block Mode, Block Address, and other control information. The DLPC410 then sends pattern data synchronously to the DMD along with row address and control information. The row cycle period is defined by the Clocks per Row in Table 11 and is synchronous with DVALID as shown in Figure 10. If DVALID is removed midway in a Row Cycle, the DLPC410 continues loading data regardless of data validity until the internal row cycle counter reaches the terminal count of Clocks/Row for that DMD.
Figure 10 is an example of a single Row Cycle for the DLP7000 DMD. A total of 32 bits of input data are presented to the DLPC410 on each clock edge (16 bits on Bus A + 16 bits on Bus B) . An entire line must be written for data to be latched into DMD memory and it requires 16 DDR clock cycles to write a single row of 1024 bits.