ZHCSJ71G april   2010  – june 2023 DLPA200

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Configurations Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics Control Logic
    6. 7.6  5-V Linear Regulator
    7. 7.7  Bias Voltage Boost Converter
    8. 7.8  Reset Voltage Buck-Boost Converter
    9. 7.9  VOFFSET/DMDVCC2 Regulator
    10. 7.10 Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 5-V Linear Regulator
      2. 8.3.2 Bias Voltage Boost Converter
      3. 8.3.3 Reset Voltage Buck-Boost Converter
      4. 8.3.4 VOFFSET/DMDVCC2 Regulator
      5. 8.3.5 Serial Communications Port (SCP)
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Component Selection Guidelines
  11. 10Power Supply Recommendations
    1. 10.1 Power Supply Rail Guidelines
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Grounding Guidelines
    2. 11.2 Thermal Considerations
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  14. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

GUID-48C333B3-EC8C-4779-99AD-899938B04CD4-low.gif Figure 6-1 PFP Package80-Pin HTQFP Top View
Table 6-1 Pin Functions
PIN I/O
(INPUT DEFAULT)(1)		 DESCRIPTION
NAME NO.
OUT00 22 Output 16 micromirror clocking waveform outputs (enabled by OE = 0).
OUT01 24 Output
OUT02 27 Output
OUT03 29 Output
OUT04 32 Output
OUT05 34 Output
OUT06 37 Output
OUT07 39 Output
OUT08 62 Output
OUT09 64 Output
OUT10 67 Output
OUT11 69 Output
OUT12 72 Output
OUT13 74 Output
OUT14 77 Output
OUT15 79 Output
A0 19 Input (pull down) Output Address. Used to select which OUTxx pin is active at a given time.
A1 18 Input (pull down)
A2 17 Input (pull down)
A3 16 Input (pull down)
MODE0 3 Input (pull down) Mode Select. Used to determine the operating mode of the DLPA200.
MODE1 2 Input (pull down)
SEL0 5 Input (pull down) Output Voltage Select. Used to switch the voltage applied to the addressed OUTxx pin.
SEL1 4 Input (pull down)
STROBE 15 Input (pull down) A rising edge on STROBE latches in the control signals after a tristate delay.
OE 6 Input (pull up) Asynchronous input controls whether the 16 OUTxx pins are active or are in a in high-impedance state.
OE = 0 : Enabled. OE = 1 : High Z.
RESET 59 Input (pull up) Resets the DLPA200 internal logic. Active low. Asynchronous.
SCPEN 58 Input (pull up) Enables serial bus data transfers. Active low.
SCPDI 57 Input (pull down) Serial bus data input. Clocked in on the falling edge of SCPCK.
SCPCK 56 Input (pull down) Serial bus clock. Provided by chipset controller.
SCPDO 42 Output Serial bus data output (open drain). Clocked out on the rising edge of SCPCK.
A 1kΩ pull up resistor to the Chip-Set Controller VDD supply is recommended.
IRQ 43 Output Interrupt request output to the chipset Controller. Active low.
A 1-kΩ pullup resistor to the Chip-Set Controller VDD supply is recommended.
DEV_ID1 45 Input (pull up)

Serial bus device address:

00 = all; 01 = device 1; 10 = device 2; 11 = device 3.
DEV_ID0 44 Input (pull up)
VBIAS 9 Output One of three specialized voltages generated by the DLPA200
VBIAS_LHI 10 Input Current limiter output for VBIAS supply (also the VBIAS switching inductor input)
VBIAS_SWL 8 Input Connection point for VBIAS supply switching inductor
VBIAS_RAIL 21, 30, 31, 40, 61, 70, 71, 80 Input The internally-used VBIAS supply rail. Internally isolated from VBIAS
VRESET 13 Output One of three specialized voltages which are generated by the DLPA200. The package thermal pad is tied to this voltage level.
VRESET_SWL 12 Input Connection point for VRESET supply switching inductor
VRESET_RAIL(1) 25, 26, 35,36, 65, 66, 75, 76 Input The internally-used VRESET supply rail. Internally isolated from VRESET.(1)
VOFFSET 49 Output One of three specialized voltages which are generated by the DLPA200
VOFFSET_RAIL 23, 28, 33, 38, 63, 68, 73, 78 Input The internally used VOFFSET supply rail. Internally isolated from VOFFSET
GND 1, 7, 14, 20, 41, 46, 53, 55, 60 GND Common ground
V5REG 47 Output The 5-volt logic supply output
P12V 11, 48, 50 Input The main power input to the DLPA200
NC 51, 52, 54 No Connect No connect
(1) The exposed thermal pad is internally connected to VRESET_RAIL.