ZHCSM38 december   2020 DAC43701 , DAC53701

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: I2C Standard Mode
    7. 7.7  Timing Requirements: I2C Fast Mode
    8. 7.8  Timing Requirements: I2C Fast Mode Plus
    9. 7.9  Timing Requirements: GPI
    10. 7.10 Timing Diagram
    11. 7.11 Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference)
    12. 7.12 Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference)
    13. 7.13 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 8.3.1.1 Reference Selection and DAC Transfer Function
          1. 8.3.1.1.1 Power Supply as Reference
          2. 8.3.1.1.2 Internal Reference
      2. 8.3.2 General-Purpose Input (GPI)
      3. 8.3.3 DAC Update
        1. 8.3.3.1 DAC Update Busy
      4. 8.3.4 Nonvolatile Memory (EEPROM or NVM)
        1. 8.3.4.1 NVM Cyclic Redundancy Check
        2. 8.3.4.2 NVM_CRC_ALARM_USER Bit
        3. 8.3.4.3 NVM_CRC_ALARM_INTERNAL Bit
      5. 8.3.5 Programmable Slew Rate
      6. 8.3.6 Power-on-Reset (POR)
      7. 8.3.7 Software Reset
      8. 8.3.8 Device Lock Feature
      9. 8.3.9 PMBus Compatibility
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Down Mode
      2. 8.4.2 Continuous Waveform Generation (CWG) Mode
      3. 8.4.3 PMBus Compatibility Mode
      4. 8.4.4 Medical Alarm Generation Mode
        1. 8.4.4.1 Low-Priority Alarm
        2. 8.4.4.2 Medium-Priority Alarm
        3. 8.4.4.3 High-Priority Alarm
        4. 8.4.4.4 Interburst Time
        5. 8.4.4.5 Pulse Off Time
        6. 8.4.4.6 Pulse On Time
    5. 8.5 Programming
      1. 8.5.1 F/S Mode Protocol
      2. 8.5.2 I2C Update Sequence
        1. 8.5.2.1 Address Byte
          1. 8.5.2.1.1 Slave Address Configuration
        2. 8.5.2.2 Command Byte
      3. 8.5.3 I2C Read Sequence
    6. 8.6 Register Map
      1. 8.6.1  STATUS Register (address = D0h) [reset = 000Ch or 0014h]
      2. 8.6.2  GENERAL_CONFIG Register (address = D1h) [reset = 01F0h]
      3. 8.6.3  CONFIG2 Register (address = D2h) [reset = 0000h]
      4. 8.6.4  TRIGGER Register (address = D3h) [reset = 0008h]
      5. 8.6.5  DAC_DATA Register (address = 21h) [reset = 0000h]
      6. 8.6.6  DAC_MARGIN_HIGH Register (address = 25h) [reset = 0000h]
      7. 8.6.7  DAC_MARGIN_LOW Register (address = 26h) [reset = 0000h]
      8. 8.6.8  PMBUS_OPERATION Register (address = 01h) [reset = 0000h]
      9. 8.6.9  PMBUS_STATUS_BYTE Register (address = 78h) [reset = 0000h]
      10. 8.6.10 PMBUS_VERSION Register (address = 98h) [reset = 2200h]
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Appliance Light Fade-In Fade-Out
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Power-Supply Margining
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Medical Alarm Generation
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  14. 13Mechanical, Packaging, and Orderable Information

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9.2.3.2 Detailed Design Procedure

For the auditory alarm implementation, two DAC53701 devices are required: one device to generate the pulse envelope and the burst, and the second device to generate the pulse frequency, as shown in Figure 9-7. The signals coming from both DACs are combined together using amplifier OP1 that has a shutdown pin, for example, the TLV9002S or OPA363. The combined signal is then ac-coupled to an audio amplifier, such as the TPA6211A1https://www.ti.com/product/TPA6211A1, to drive the speaker. The TPA6211A1 is an integrated Class-AB amplifier that can drive up to 3 W of output power with very little distortion. As per medical alarm standard IEC60601-1-8, the pulse frequency must be greater than 150 Hz, and must have at least four harmonic components that are within ±15 dB of each other. As a result of the square-wave pulse frequency and the mixing done by OP1, the speaker output generates multiple harmonics of the fundamental pulse frequency. The DACx3701 provide a range of timing options for the pulse frequency and envelope, and various options to program the pulse frequency and envelope timings. See Section 8.4.4 for the alarm configuration options. Calculate the frequency of a square wave or pulse frequency using Equation 3. The square-wave function has a limited number of frequencies because this function is programmed by the SLEW_RATE bit alone. To get a higher number of frequencies, generate a triangular waveform with comparator mode output. Generate the triangular waveform using Equation 4. Set the DAC output in the comparator mode by fixing the FB pin to the midscale of the DAC using a resistive voltage divider from VDD. Select VDD as the reference in this case using the GENERAL_CONFIG register (see Section 8.6.2).

The following pseudocode helps to get started with a medical alarm application using two DACs:

//SYNTAX: WRITE <REGISTER NAME (Hex code)>, <MSB DATA>, <LSB DATA>
//Power-up the first DAC, enable VDD reference
//SLEW_RATE: 1.6384 ms (Square wave frequency: 610 Hz)
WRITE GENERAL_CONFIG(0xD1), 0xD1, 0x58
//Set MARGIN_HIGH on the first DAC
WRITE DAC_MARGIN_HIGH(0x25), 0x0F, 0xFC
//Set MARGIN_LOW on the first DAC
WRITE DAC_MARGIN_LOW(0x26), 0x00, 0x00
//Trigger square wave generation on the first DAC
WRITE TRIGGER(0xD3), 0x01, 0x00
//Power-up the second DAC, enable VDD reference
//CODE_STEP: 8 LSB, SLEW_RATE: 204.8 µs x 1.75 = 358.4 µs (Envelope rise/fall times for full-scale: ~26 ms)
WRITE GENERAL_CONFIG(0xD1), 0x1A, 0xE8
//OPTION-1: Configure the second DAC for low-priority alarm with minimum time settings and trigger
WRITE CONFIG2(0xD2), 0x01, 0x00
//OPTION-2: Configure the second DAC for medium-priority alarm with minimum time settings and trigger
WRITE CONFIG2(0xD2), 0x02, 0x00
//OPTION-3: Configure the second DAC for high-priority alarm with minimum time settings and trigger
WRITE CONFIG2(0xD2), 0x04, 0x00
//Set MARGIN_HIGH on the second DAC
WRITE DAC_MARGIN_HIGH(0x25), 0x0F, 0xFC
//Set MARGIN_LOW on the second DAC
WRITE DAC_MARGIN_LOW(0x26), 0x00, 0x00