ZHCSNS5A April   2021  – December 2021 DAC53004 , DAC63004

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. 引脚配置和功能
  6. 规格
    1. 6.1  绝对最大额定值
    2. 6.2  ESD 等级
    3. 6.3  建议的操作条件
    4. 6.4  热性能信息
    5. 6.5  电气特性:电压输出
    6. 6.6  电气特性:电流输出
    7. 6.7  电气特性:比较器模式
    8. 6.8  电气特性:通用
    9. 6.9  时序要求:I2C 标准模式
    10. 6.10 时序要求:I2C 快速模式
    11. 6.11 时序要求:I2C 超快速模式
    12. 6.12 时序要求:SPI 写入操作
    13. 6.13 时序要求:SPI 读取和菊花链操作 (FSDO = 0)
    14. 6.14 时序要求:SPI 读取和菊花链操作 (FSDO = 1)
    15. 6.15 时序要求:GPIO
    16. 6.16 时序图
    17. 6.17 典型特性:电压输出
    18. 6.18 典型特性:电流输出
    19. 6.19 典型特性:比较器
    20. 6.20 典型特性:通用
  7. 详细说明
    1. 7.1 Overview
    2. 7.2 功能方框图
    3. 7.3 特性说明
      1. 7.3.1 智能数模转换器 (DAC) 架构
      2. 7.3.2 数字输入/输出
      3. 7.3.3 非易失性存储器 (NVM)
      4. 7.3.4 Power Consumption
    4. 7.4 器件功能模式
      1. 7.4.1 电压输出模式
        1. 7.4.1.1 电压基准和 DAC 传递函数
          1. 7.4.1.1.1 内部基准
          2. 7.4.1.1.2 外部基准
          3. 7.4.1.1.3 电源作为基准
      2. 7.4.2 电流输出模式
      3. 7.4.3 比较器模式
        1. 7.4.3.1 可编程迟滞比较器
        2. 7.4.3.2 可编程窗口比较器
      4. 7.4.4 故障转储模式
      5. 7.4.5 应用特定模式
        1. 7.4.5.1 电压裕量和调节
          1. 7.4.5.1.1 高阻抗输出和 PROTECT 输入
          2. 7.4.5.1.2 可编程转换率控制
          3. 7.4.5.1.3 PMBus 兼容模式
        2. 7.4.5.2 函数生成
          1. 7.4.5.2.1 三角波形生成
          2. 7.4.5.2.2 锯齿波形生成
          3. 7.4.5.2.3 正弦波形生成
      6. 7.4.6 器件复位和故障管理
        1. 7.4.6.1 上电复位 (POR)
        2. 7.4.6.2 外部复位
        3. 7.4.6.3 寄存器映射锁定
        4. 7.4.6.4 NVM 循环冗余校验 (CRC)
          1. 7.4.6.4.1 NVM-CRC-FAIL-USER 位
          2. 7.4.6.4.2 NVM-CRC-FAIL-INT 位
      7. 7.4.7 Power-Down Mode
        1. 7.4.7.1 Deep-Sleep Mode
    5. 7.5 编程
      1. 7.5.1 SPI 编程模式
      2. 7.5.2 I2C 编程模式
        1. 7.5.2.1 F/S 模式协议
        2. 7.5.2.2 I2C 更新序列
          1. 7.5.2.2.1 地址字节
          2. 7.5.2.2.2 命令字节
        3. 7.5.2.3 I2C 读取序列
      3. 7.5.3 通用输入/输出 (GPIO) 模式
    6. 7.6 寄存器映射
      1. 7.6.1  NOP 寄存器(地址 = 00h)[复位 = 0000h]
      2. 7.6.2  DAC-X-MARGIN-HIGH 寄存器(地址 = 01h、07h、0Dh、13h)[复位 = 0000h]
      3. 7.6.3  DAC-X-MARGIN-LOW 寄存器(地址 = 02h、08h、0Eh、14h)[复位 = 0000h]
      4. 7.6.4  DAC-X-VOUT-CMP-CONFIG 寄存器(地址 = 03h、09h、0Fh、15h)[复位 = 0000h]
      5. 7.6.5  DAC-X-IOUT-MISC-CONFIG 寄存器(地址 = 04h、0Ah、10h、16h)[复位 = 0000h]
      6. 7.6.6  DAC-X-CMP-MODE-CONFIG 寄存器(地址 = 05h、0Bh、11h、17h)[复位 = 0000h]
      7. 7.6.7  DAC-X-FUNC-CONFIG 寄存器(地址 = 06h、0Ch、12h、18h)[复位 = 0000h]
      8. 7.6.8  DAC-X-DATA 寄存器(地址 = 19h、1Ah、1Bh、1Ch)[复位 = 0000h]
      9. 7.6.9  COMMON-CONFIG 寄存器(地址 = 1Fh)[复位 = 0FFFh]
      10. 7.6.10 COMMON-TRIGGER 寄存器(地址 = 20h)[复位 = 0000h]
      11. 7.6.11 COMMON-DAC-TRIG 寄存器(地址 = 21h)[复位 = 0000h]
      12. 7.6.12 GENERAL-STATUS 寄存器(地址 = 22h)[复位 = 00h、DEVICE-ID、VERSION-ID]
      13. 7.6.13 CMP-STATUS 寄存器(地址 = 23h)[复位 = 0000h]
      14. 7.6.14 GPIO-CONFIG 寄存器(地址 = 24h)[复位 = 0000h]
      15. 7.6.15 DEVICE-MODE-CONFIG 寄存器(地址 = 25h)[复位 = 0000h]
      16. 7.6.16 INTERFACE-CONFIG 寄存器(地址 = 26h)[复位 = 0000h]
      17. 7.6.17 SRAM-CONFIG 寄存器(地址 = 2Bh)[复位 = 0000h]
      18. 7.6.18 SRAM-DATA 寄存器(地址 = 2Ch)[复位 = 0000h]
      19. 7.6.19 DAC-X-DATA-8BIT 寄存器(地址 = 40h、41h、42h、43h)[复位 = 0000h]
      20. 7.6.20 BRDCAST-DATA 寄存器(地址 = 50h)[复位 = 0000h]
      21. 7.6.21 PMBUS-PAGE 寄存器 [复位 = 0300h]
      22. 7.6.22 PMBUS-OP-CMD-X 寄存器 [复位 = 0000h]
      23. 7.6.23 PMBUS-CML 寄存器 [复位 = 0000h]
      24. 7.6.24 PMBUS-VERSION 寄存器 [复位 = 2200h]
  8. 应用和实现
    1. 8.1 应用信息
    2. 8.2 典型应用
      1. 8.2.1 设计要求
      2. 8.2.2 详细设计过程
      3. 8.2.3 应用曲线
  9. 电源相关建议
  10. 10布局
    1. 10.1 布局指南
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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Overview

The 12-bit DAC63004 and 10-bit DAC53004 (DACx3004) are a pin-compatible family of ultra-low-power, quad-channel, buffered voltage-output and current-output, smart digital-to-analog converters (DACs). The DAC channels are independently configurable as voltage output or current output. The DAC outputs change to Hi-Z when VDD is off; a feature useful in voltage-margining applications. These smart DACs contain nonvolatile memory (NVM), an internal reference, automatically detectable I2C and SPI interface, PMBus-compatibility in I2C mode, a force-sense output, and a general-purpose input/output. These devices support Hi-Z power-down modes by default, which can also be configured to 10 kΩ-GND or 100 kΩ-GND using the NVM. The DACx3004 have a power-on-reset (POR) circuit that makes sure all the registers start with default or user-programmed settings using NVM. The DACx3004 operate with either an internal reference, external reference, or with a power supply as the reference, and provide a full-scale output between 1.8 V and 5.5 V.

The DACx3004 devices support I2C standard mode (100 kbps), fast mode (400 kbps), and fast mode plus (1 Mbps). The I2C interface can be configured with four target addresses using the A0 pin. These devices also support specific PMBus commands such as turn on/off, margin high or low, and more. SPI mode supports a three-wire interface by default, with up to a 50-MHz SCLK input. The GPIO input can be configured as SDO in the NVM for SPI read capability. The GPIO input can also be configured as FAULT-DUMP, LDAC, PD, PROTECT, RESET, and STATUS functions. These devices support deep-sleep mode in addition to sleep (power-down) mode. Deep-sleep mode uses the GPIO pin for power-down and wake up, in which the device draws a very-low power-down current of 3 μA. Together with ultra-low-power operation, the DACx3004 are designed for battery-operated applications, such as land mobile radios, medical pulse oximeters, and laptops.

The DACx3004 also include digital slew rate control, and support standard waveform generation such as sine and cosine, triangular, and sawtooth. These devices can generate pulse-width modulation (PWM) output with the combination of the triangular or sawtooth waveform and the FB pin. The force-sense outputs of the DAC channels can be used as programmable comparators. Comparator mode allows programmable hysteresis, latching comparator, and window comparator. These features enable the DACx3004 to go beyond the limitations of a conventional DAC that depends on a processor to function. As a result of processor-less operation and the smart feature set, the DACx3004 are called smart DACs.