ZHCSPG5 December   2021 DAC11001B

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: Write, 4.5 V ≤ DVDD ≤ 5.5 V
    7. 6.7  Timing Requirements: Write, 2.7 V ≤ DVDD < 4.5 V
    8. 6.8  Timing Requirements: Read and Daisy-Chain Write, 4.5 V ≤ DVDD ≤ 5.5 V
    9. 6.9  Timing Requirements: Read and Daisy-Chain Write, 2.7 V ≤ DVDD < 4.5 V
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter Architecture
      2. 7.3.2 External Reference
      3. 7.3.3 Output Buffers
      4. 7.3.4 Internal Power-On Reset (POR)
      5. 7.3.5 Temperature Drift and Calibration
      6. 7.3.6 DAC Output Deglitch Circuit
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fast-Settling Mode and THD
      2. 7.4.2 DAC Update Rate Mode
    5. 7.5 Programming
      1. 7.5.1 Daisy-Chain Operation
      2. 7.5.2 CLR Pin Functionality and Software Clear
      3. 7.5.3 Output Update (Synchronous and Asynchronous)
        1. 7.5.3.1 Synchronous Update
        2. 7.5.3.2 Asynchronous Update
      4. 7.5.4 Software Reset Mode
    6. 7.6 Register Map
      1. 7.6.1 NOP Register (address = 00h) [reset = 0x000000h for bits [23:0]]
      2. 7.6.2 DAC-DATA Register (address = 01h) [reset = 0x000000h for bits [23:0]]
      3. 7.6.3 CONFIG1 Register (address = 02h) [reset = 004C80h for bits [23:0]]
      4. 7.6.4 DAC-CLEAR-DATA Register (address = 03h) [reset = 000000h for bits [23:0]]
      5. 7.6.5 TRIGGER Register (address = 04h) [reset = 000000h for bits [23:0]]
      6. 7.6.6 STATUS Register (address = 05h) [reset = 000000h for bits [23:0]]
      7. 7.6.7 CONFIG2 Register (address = 06h) [reset = 000040h for bits [23:0]]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Source Measure Unit (SMU)
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 High-Precision Control Loop
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Arbitrary Waveform Generation (AWG)
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Interfacing to a Processor
      2. 8.3.2 Interfacing to a Low-Jitter LDAC Source
      3. 8.3.3 Embedded Resistor Configurations
        1. 8.3.3.1 Minimizing Bias Current Mismatch
        2. 8.3.3.2 2x Gain Configuration
        3. 8.3.3.3 Generating Negative Reference
    4. 8.4 What to Do and What Not to Do
      1. 8.4.1 What to Do
      2. 8.4.2 What Not to Do
    5. 8.5 Initialization Set Up
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Supply Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Assembly Effects on Precision
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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6.5 Electrical Characteristics

at TA = –40°C to +125°C, VCC = +15 V, VSS = –15 V, AVDD = 5.5 V, DVDD = 3.3 V, IOVDD = 1.8 V, see note(1) for VREFPF and VREFNF, OUT pin buffered with unity gain OPA827, ROFS, RCM, RFB unconnected, and all typical specifications at TA = 25°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
Resolution 20 Bits
INL Relative accuracy(2)(3) TA = 0°C to 70°C(4) 
VREFPF = 10 V and VREFNF = 0 V
VREFPF = +5 V and VREFNF = –5 V		 –1 1 LSB
TA = 0°C to 70°C(4) –1.25 1.25
TA = –40°C to +125°C –2 2
Relative accuracy drift over time(2) TA = 25°C, 1000 hrs ±0.1 LSB
DNL Differential nonlinearity(2)(3) TA = –40°C to +125°C –1 1 LSB
Zero code error(4) TA = 0°C to 70°C, code 0d into DAC,
unipolar ranges only		 –4 4 LSB
TA = –40°C to +125°C, code 0d into DAC,
unipolar ranges only		 –4 4
TA = 25°C, unipolar ranges only ±2
Zero code error temperature coefficient TA = 0°C to 70°C, code 0d into DAC,
unipolar ranges only		 ±0.04 ppm FSR/°C
TA = –40°C to +125°C, code 0d into DAC,
unipolar ranges only		 ±0.04
Gain error(2)(4) TA = 0°C to 70°C –8 8 ppm of FSR
TA = –40°C to +125°C –10 10
TA = 25°C ±2
Gain error temperature coefficient TA = 0°C to 70°C ±0.04 ppm FSR/°C
TA = –40°C to +125°C ±0.04
Positive full-scale error(4) TA = 0°C to 70°C, code 1048575d into DAC –8 8 LSB
TA = –40°C to +125°C, code 1048575d into DAC –10 10
TA = 25°C, code 1048575d into DAC ±2
Full-scale error temperature coefficient TA = 0°C to 70°C ±0.04 ppm FSR/°C
TA = –40°C to +125°C ±0.04
OUTPUT CHARACTERISTICS
Headroom From VREFPF to VCC 5 V
Footroom From VREFNF to VSS 5 V
DC impedance From ROFS to RCM 5 kΩ
From RCM to RFB 5
ZO DC output impedance 2.5 kΩ
Power supply rejection ratio (dc) VCC = 15 V ±20%, VSS = –15 V 1.5 µV/V
VCC = 15 V, VSS = –15 V ±20% 1
Output voltage drift over time TA = 25°C, VOUT = midscale, 1000 hr 1 ppm of FSR
VOLTAGE REFERENCE INPUT
Reference input impedance (REFPF) DAC at midscale,
VREFPF = 10 V, VREFNF = 0 V		 5.5 kΩ
Reference input impedance (REFNF) DAC at midscale,
VREFPF = 10 V, VREFNF = 0 V		 7
DYNAMIC PERFORMANCE
ts Output voltage settling time(5) Full-scale settling to 0.1%FSR,
VREFPF = 10 V, VREFNF = 0 V		 1 µs
Full-scale settling to ±1 LSB,
VREFPF = 10 V, VREFNF = 0 V		 3
1-mV step settling to ±1 LSB,
VREFPF = 10 V, VREFNF = 0 V		 2.5
SR Slew rate(6) Full-scale step, measured at OUT pin,
VREFPF = 10 V, VREFNF = 0 V		 30 V/µs
Power-on glitch magnitude Measured at unbuffered DAC voltage output,
VREFPF = 10 V, VREFNF = 0 V		 –0.2 V
Vn Output noise 0.1-Hz to 10-Hz, DAC at midscale,
VREFPF = 10 V, VREFNF = 0 V		 0.4 µVpp
100-kHz bandwidth, DAC at midscale,
VREFPF = 10 V, VREFNF = 0 V		 3 µVrms
Output noise density Measured at 1 kHz, 10 kHz, 100 kHz,
DAC at mid scale,
VREFPF = 10 V, VREFNF = 0 V		 7 nV/√Hz
SFDR Spurious free dynamic range(6) DAC update rate = 768 kHz, fOUT = 1 kHz,
VREFPF = 4.5 V, VREFNF = –4.5 V,
sixth-order, low-pass, 30-kHz output filter		 –120 dB
DAC update rate = 768 kHz, fOUT = 20 kHz,
VREFPF = 4.5 V, VREFNF = –4.5 V,
sixth-order, low-pass, 30-kHz output filter		 –114
DAC update rate = 1 MHz, fOUT = 100 kHz,
VREFPF = 4.5 V, VREFNF = –4.5 V,
sixth-order, low-pass, 150-kHz output filter		 –92
THD Total harmonic distortion(6) DAC update rate = 768 kHz, fOUT = 1 kHz,
VREFPF = 4.5 V, VREFNF = –4.5 V,
sixth-order, low-pass, 30-kHz output filter		 –118 dB
DAC update rate = 768 kHz, fOUT = 20 kHz,
VREFPF = 4.5 V, VREFNF = –4.5 V,
sixth-order, low-pass, 30-kHz output filter		 –118
DAC update rate = 1 MHz, fOUT = 100 kHz,
VREFPF = 4.5 V, VREFNF = –4.5 V,
sixth-order, low-pass, 150-kHz output filter		 –96
Power supply rejection ratio (ac) 200-mV, 50-Hz or 60-Hz sine wave
superimposed on VSS, VCC = 15 V		 95 dB
200-mV, 50 Hz or 60 Hz sine wave
superimposed on VCC, VSS = –15 V		 95
Code change glitch impulse ±1 LSB change around mid code (including feedthrough), VREFPF = 10 V, VREFNF = 0 V,
measured at output of buffer op amp		 1 nV-s
Code change glitch impulse magnitude ±1 LSB change around mid code (including feedthrough), VREFPF = 10 V, VREFNF = 0  V,
measured at output of buffer op amp		 5 mV
Reference feedthrough VREFPF = 10 V ± 10%, VREFNF = 0 V,
frequency = 100 Hz, DAC at zero scale		 –90 dB
VREFNF = –10 V ± 10%, VREFPF = 10 V,
frequency = 100 Hz, DAC at full scale		 –90
Digital feedthrough SCLK = 1 MHz, DAC static at midscale,
VREFPF = 10 V, VREFNF = 0 V		 1 nV-s
DIGITAL INPUTS
Hysteresis voltage 0.4 V
Input current ±5 µA
Pin capacitance Per pin 10 pF
DIGITAL OUTPUTS
VOL Low-level output voltage Sinking 200 µA 0.4 V
VOH High-level output voltage Sourcing 200 µA IOVDD – 0.5 V
High impedance leakage ±5 µA
High impedance output capacitance 10 pF
POWER
IAVDD Current flowing into AVDD VREFPF = 10 V, VREFNF = 0 V, midscale code 2.5 mA
IVCC Current flowing into VCC VREFPF = 10 V, VREFNF = 0 V, midscale code 15 mA
IVSS Current flowing into VSS VREFPF = 10 V, VREFNF = 0 V, midscale code 15 mA
IDVDD Current flowing into DVDD VREFPF = 10 V, VREFNF = 0 V, midscale code 0.5 mA
IIOVDD Current flowing into IOVDD VREFPF = 10 V, VREFNF = 0 V, midscale code,
all digital input pins static at IOVDD		 0.1 mA
IREFPF Reference input current (VREFPF) VREFPF = 10 V, VREFNF = 0 V, midscale code 7 mA
IREFNF Reference input current (VREFNF) VREFPF = 10 V, VREFNF = 0 V, midscale code 7 mA
(1) Specified for the following pairs: VREFPF = 5 V and VREFNF = 0 V; VREFPF = 10 V and VREFNF = 0 V; VREFPF = 5 V and VREFNF = –5 V; VREFPF = 10 V and VREFNF = –10 V.
(2) Calculated between code 0d to 1048575d.
(3) With device temperature calibration mode enabled and used.
(4) Specified by design, not production tested.
(5) Adaptive TnH mode. TnH action is disabled for large code steps. For small steps, TnH action happens with a hold time of 1.2 µs.
(6) OUT pin buffered with unity gain OPA828.