ZHCSEI7B December 2015 – December 2017 CSD95377Q4M
PRODUCTION DATA.
The UVLO comparator evaluates the VDD voltage level. As VVDD rises, both the control FET and sync FET gates hold actively low at all times until VVDD reaches the higher UVLO threshold (VUVLO_H). Then the driver becomes operational and responds to PWM and SKIP# commands. If VDD falls below the lower UVLO threshold (VUVLO_L = VUVLO_H – hysteresis), the device disables the driver and drives the outputs of the control FET and Sync FET gates actively low. Figure 1 shows this function.
CAUTION
Do not start the driver in the very-low power mode (SKIP# = Tri-state).