ZHCSEO0B February   2016  – April 2018 CSD87335Q3D

PRODUCTION DATA.  

  1. 1特性
  2. 2应用
  3. 3说明
    1.     俯视图
      1.      Device Images
  4. 4修订历史记录
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Power Block Performance
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Power Block Device Characteristics
    7. 5.7 Typical Power Block MOSFET Characteristics
  6. 6Applications and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Equivalent System Performance
    2. 6.2 Power Loss Curves
    3. 6.3 Safe Operating Curves (SOA)
    4. 6.4 Normalized Curves
    5. 6.5 Calculating Power Loss and SOA
      1. 6.5.1 Design Example
      2. 6.5.2 Calculating Power Loss
      3. 6.5.3 Calculating SOA Adjustments
  7. 7Recommended PCB Design Overview
    1. 7.1 Electrical Performance
    2. 7.2 Thermal Performance
  8. 8器件和文档支持
    1. 8.1 接收文档更新通知
    2. 8.2 社区资源
    3. 8.3 商标
    4. 8.4 静电放电警告
    5. 8.5 Glossary
  9. 9机械、封装和可订购信息
    1. 9.1 Q3D 封装尺寸
    2. 9.2 焊盘布局建议
    3. 9.3 模板建议
    4. 9.4 Q3D 卷带信息
    5. 9.5 引脚配置

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.1 Electrical Performance

The power block has the ability to switch voltages at rates greater than 10 kV/µs. Special care must be then taken with the PCB layout design and placement of the input capacitors, driver IC, and output inductor.

  • The placement of the input capacitors relative to the power block’s VIN and PGND pins should have the highest priority during the component placement routine. It is critical to minimize these node lengths. As such, ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 33). The example in Figure 33 uses 6 × 10-µF ceramic capacitors (TDK Part # C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the power block, C5, C7, C19, and C8 should follow in order.
  • The driver IC should be placed relatively close to the power block gate pins. TG and BG should connect to the outputs of the driver IC. The TGR pin serves as the return path of the high-side gate drive circuitry and should be connected to the phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap capacitor for the driver IC will also connect to this pin.
  • The switching node of the output inductor should be placed relatively close to the power block VSW pins. Minimizing the node length between these two components will reduce the PCB conduction losses and actually reduce the switching noise level. In the event the switch node waveform exhibits ringing that reaches undesirable levels, the use of a boost resistor or RC snubber can be an effective way to easily reduce the peak ring level. The recommended boost resistor value will range between 1 Ω to 4.7 Ω depending on the output characteristics of driver IC used in conjunction with the power block. The RC snubber values can range from 0.5 Ω to 2.2 Ω for the R and 330 pF to 2200 pF for the C. Please refer to Snubber Circuits: Theory, Design and Application (SLUP100) for more details on how to properly tune the RC snubber values. The RC snubber should be placed as close as possible to the Vsw node and PGND (see Figure 33). (1)
    • 1. Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of Missouri – Rolla