ZHCSP11 May   2022 CDCBT1001

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Down Tolerant Input
      2. 7.3.2 Up Conversion
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Processor Clock Up Translation
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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5 Pin Configuration and Functions



Figure 5-1 DPW Package 5-Pin X2SON Transparent Top View
Table 5-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
CLK_IN1IClock input. LVCMOS input clock is injected into this pin. The acceptable LVCMOS voltage level is defined by VDD_IN.
CLK_OUT4OClock output. This pin outputs LVCMOS clock. The output LVCMOS voltage level is defined by VDD_OUT
VDD_IN5PInput supply voltage. 1.08 V ≤ VDD_IN ≤ 1.32 V.
VDD_OUT2POutput supply voltage. 1.62 V ≤ VDD_OUT ≤ 1.98 V.
GND3GGround
(1) I = Input, O = Output, P = Power, G = Ground