To begin the design process, determine the following:
- Input clock
- The supply voltage on VDD_IN will determine the input clock voltage range.
- For a valid logic-high, the high level clock input must exceed VIH spec. For a valid logic-low, the low level clock input must be below VIL.
- Some specifications such as duty cycle and phase noise have additional requirements for VIH, VIL, input swing and input slew rate. Refer to the test conditions column in the Electrical Characteristics table.
- Output clock
- The supply voltage on VDD_OUT will determine the output clock voltage range.