ZHCSM61C November   2014  – September 2020 CC3200MOD

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Functional Block Diagrams
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 CC3200MOD Pin Diagram
    2. 7.2 Pin Attributes
      1. 7.2.1 Module Pin Attributes
    3. 7.3 Pin Attributes and Pin Multiplexing
    4. 7.4 Recommended Pin Multiplexing Configurations
      1. 7.4.1 ADC Reference Accuracy Specifications
    5. 7.5 Drive Strength and Reset States for Analog-Digital Multiplexed Pins
    6. 7.6 Pad State After Application of Power to Chip, but Before Reset Release
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Power Consumption Summary
      1. 8.5.1 Current Consumption
    6. 8.6  Brownout and Blackout Conditions
    7. 8.7  WLAN RF Characteristics
      1. 8.7.1 WLAN Receiver Characteristics
      2. 8.7.2 WLAN Transmitter Characteristics
    8. 8.8  Reset Requirement
    9. 8.9  Thermal Resistance Characteristics for MOB and MON Packages
    10. 8.10 Timing and Switching Characteristics
      1. 8.10.1 nRESET
      2. 8.10.2 Wake Up From Hibernate Timing
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Arm® Cortex®-M4 处理器内核子系统
    4. 9.4 CC3200 Device Encryption
    5. 9.5 Wi-Fi® Network Processor Subsystem
    6. 9.6 Power-Management Subsystem
      1. 9.6.1 VBAT Wide-Voltage Connection
    7. 9.7 Low-Power Operating Mode
    8. 9.8 Memory
      1. 9.8.1 External Memory Requirements
      2. 9.8.2 Internal Memory
        1. 9.8.2.1 SRAM
        2. 9.8.2.2 ROM
        3. 9.8.2.3 Memory Map
    9. 9.9 Boot Modes
      1. 9.9.1 Overview
      2. 9.9.2 Invocation Sequence and Boot Mode Selection
      3. 9.9.3 Boot Mode List
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2 Reset
      3. 10.1.3 Unused Pins
      4. 10.1.4 General Layout Recommendations
      5. 10.1.5 Do's and Don'ts
    2. 10.2 Reference Schematics
    3. 10.3 Design Requirements
    4. 10.4 Detailed Design Procedure
    5. 10.5 Layout Recommendations
      1. 10.5.1 RF Section (Placement and Routing)
      2. 10.5.2 Antenna Placement and Routing
      3. 10.5.3 Transmission Line
  11. 11Environmental Requirements and Specifications
    1. 11.1 PCB Bending
    2. 11.2 Handling Environment
      1. 11.2.1 Terminals
      2. 11.2.2 Falling
    3. 11.3 Storage Condition
      1. 11.3.1 Moisture Barrier Bag Before Opened
      2. 11.3.2 Moisture Barrier Bag Open
    4. 11.4 Baking Conditions
    5. 11.5 Soldering and Reflow Condition
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
      2. 12.1.2 Firmware Updates
    2. 12.2 Device Nomenclature
    3. 12.3 Documentation Support
    4. 12.4 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical Drawing
    2. 13.2 Package Option
      1. 13.2.1 Packaging Information
      2. 13.2.2 Tape and Reel Information

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • MOB|63
散热焊盘机械数据 (封装 | 引脚)

8.5.1 Current Consumption

TA = 25 °C, VBAT = 3.6 V
PARAMETERTEST CONDITIONS(1)(5)MINTYPMAXUNIT
MCU ACTIVENWP ACTIVETX1 DSSSTX power level = 0278mA
TX power level = 4194
6 OFDMTX power level = 0254
TX power level = 4185
54 OFDMTX power level = 0229
TX power level = 4166
RX1 DSSS59
54 OFDM59
NWP idle connected(3)15.3
MCU SLEEPNWP ACTIVETX1 DSSSTX power level = 0275mA
TX power level = 4191
6 OFDMTX power level = 0251
TX power level = 4182
54 OFDMTX power level = 0226
TX power level = 4163
RX1 DSSS56
54 OFDM56
NWP idle connected(3)12.2
MCU LPDSNWP activeTX1 DSSSTX power level = 0272mA
TX power level = 4188
6 OFDMTX power level = 0248
TX power level = 4179
54 OFDMTX power level = 0223
TX power level = 4160
RX1 DSSS53
54 OFDM53
NWP LPDS(2)0.275
NWP idle connected(3)0.875
MCU hibernateNWP hibernate7µA
Peak calibration current (4)VBAT = 3.3 V450mA
VBAT = 2.3 V620
(1) TX power level = 0 implies maximum power (see Figure 8-1 through Figure 8-3). TX power level = 4 implies output power backed off approximately 4 dB.
(2) The LPDS number reported is with retention of 64KB MCU SRAM. The CC3200 device can be configured to retain 0KB, 64KB, 128KB, 192KB or 256KB SRAM in LPDS. Each 64KB retained increases LPDS current by 4 µA.
(3) DTIM = 1
(4) The complete calibration can take up to 17 mJ of energy from the battery over a time of 24 ms. Calibration is performed sparingly, typically when coming out of Hibernate and only if temperature has changed by more than 20°C or the time elapsed from prior calibration is greater than 24 hours.
(5) The CC3200 system is a constant power-source system. The active current numbers scale based on the VBAT voltage supplied.
GUID-27D3827A-D363-41EC-82B9-2B92FAEB480B-low.png
Note: The area enclosed in the circle represents a significant reduction in current when transitioning from TX power level 3 to 4. In the case of lower range requirements (13-dBm output power), TI recommends using TX power level 4 to reduce the current.
Figure 8-1 TX Power and IBAT vs TX Power Level Settings (1 DSSS)

 

GUID-19D02332-50F5-4611-993F-53E3C6D98723-low.pngFigure 8-2 TX Power and IBAT vs TX Power Level Settings (6 OFDM)
GUID-9E5C411F-AA89-4910-8DFE-134BD2F1C9F6-low.pngFigure 8-3 TX Power and IBAT vs TX Power Level Settings (54 OFDM)