ZHCSSG0B December   2022  – April 2024 CC1314R10

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 功能方框图
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagram—RGZ Package (Top View)
    2. 6.2 Signal Descriptions—RGZ Package
    3. 6.3 Connections for Unused Pins and Modules—RGZ Package
    4. 6.4 Pin Diagram—RSK Package (Top View)
    5. 6.5 Signal Descriptions—RSK Package
    6. 6.6 Connection of Unused Pins and Module—RSK Package
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Power Supply and Modules
    5. 7.5  Power Consumption—Power Modes
    6. 7.6  Power Consumption—Radio Modes
    7. 7.7  Nonvolatile (Flash) Memory Characteristics
    8. 7.8  Thermal Resistance Characteristics
    9. 7.9  RF Frequency Bands
    10. 7.10 861MHz to 1054MHz—Receive (RX)
    11. 7.11 861MHz to 1054MHz—Transmit (TX) 
    12. 7.12 861MHz to 1054MHz - PLL Phase Noise Wideband Mode
    13. 7.13 861MHz to 1054MHz - PLL Phase Noise Narrowband Mode
    14. 7.14 Timing and Switching Characteristics
      1. 7.14.1 Reset Timing
      2. 7.14.2 Wakeup Timing
      3. 7.14.3 Clock Specifications
        1. 7.14.3.1 48MHz Clock Input (TCXO)
        2. 7.14.3.2 48MHz Crystal Oscillator (XOSC_HF)
        3. 7.14.3.3 48MHz RC Oscillator (RCOSC_HF)
        4. 7.14.3.4 2MHz RC Oscillator (RCOSC_MF)
        5. 7.14.3.5 32.768 kHz Crystal Oscillator (XOSC_LF)
        6. 7.14.3.6 32 kHz RC Oscillator (RCOSC_LF)
      4. 7.14.4 Serial Peripheral Interface (SPI) Characteristics
        1. 7.14.4.1 SPI Characteristics
        2. 7.14.4.2 SPI Master Mode
        3. 7.14.4.3 SPI Master Mode Timing Diagrams
        4. 7.14.4.4 SPI Slave Mode
        5. 7.14.4.5 SPI Slave Mode Timing Diagrams
      5. 7.14.5 UART
        1. 7.14.5.1 UART Characteristics
    15. 7.15 Peripheral Characteristics
      1. 7.15.1 ADC
        1. 7.15.1.1 Analog-to-Digital Converter (ADC) Characteristics
      2. 7.15.2 DAC
        1. 7.15.2.1 Digital-to-Analog Converter (DAC) Characteristics
      3. 7.15.3 Temperature and Battery Monitor
        1. 7.15.3.1 Temperature Sensor
        2. 7.15.3.2 Battery Monitor
      4. 7.15.4 Comparators
        1. 7.15.4.1 Low-Power Clocked Comparator
        2. 7.15.4.2 Continuous Time Comparator
      5. 7.15.5 Current Source
        1. 7.15.5.1 Programmable Current Source
      6. 7.15.6 GPIO
        1. 7.15.6.1 GPIO DC Characteristics
    16. 7.16 Typical Characteristics
      1. 7.16.1 MCU Current
      2. 7.16.2 RX Current
      3. 7.16.3 TX Current
      4. 7.16.4 RX Performance
      5. 7.16.5 TX Performance
      6. 7.16.6 ADC Performance
  9. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  System CPU
    3. 8.3  Radio (RF Core)
      1. 8.3.1 Proprietary Radio Formats
    4. 8.4  Memory
    5. 8.5  Sensor Controller
    6. 8.6  Cryptography
    7. 8.7  Timers
    8. 8.8  Serial Peripherals and I/O
    9. 8.9  Battery and Temperature Monitor
    10. 8.10 µDMA
    11. 8.11 Debug
    12. 8.12 Power Management
    13. 8.13 Clock Systems
    14. 8.14 Network Processor
  10. 9 Application, Implementation, and Layout
    1. 9.1 Reference Designs
    2. 9.2 Junction Temperature Calculation
  11. 10Device and Documentation Support
    1. 10.1 Tools and Software
      1. 10.1.1 SimpleLink™ Microcontroller Platform
    2. 10.2 Documentation Support
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information

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7.14.4.2 SPI Master Mode

over operating free-air temperature range (unless otherwise noted).
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
tSCLK_H/L SCLK High or Low time (tSPI/2) - 1 tSPI / 2 (tSPI/2) + 1 ns
tCS.LEAD CS lead-time, CS active to clock 1 SCLK
tCS.LAG CS lag time, Last clock to CS inactive 1 SCLK
tCS.ACC CS access time, CS active to MOSI data out 1 SCLK
tCS.DIS CS disable time, CS inactive to MOSI high inpedance 1 SCLK
tSU.MI MISO input data setup time(1) VDDS = 3.3V 12.5 ns
tSU.MI MISO input data setup time VDDS = 1.8V 23.5 ns
tHD.MI MISO input data hold time 0 ns
tVALID.MO MOSI output data valid time(2) SCLK edge to MOSI valid,CL = 20 pF (4) 13 ns
tHD.MO MOSI output data hold time(3) CL = 20 pF 0 ns
(1) The MISO input data setup time can be fully compensated when delayed sampling feature is enabled.
(2) Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge.
(3) Specifies how long data on the output is valid after the output changing SCLK clock edge.