ZHCSDC8A December 2014 – November 2017
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DPDM_EN | TMR2X_EN | BATFET_Disable | JEITA_VSET | Reserved | Reserved | INT_MASK[1] | INT_MASK[0] |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
BIT | FIELD | TYPE | RESET | DESCRIPTION | NOTE |
---|---|---|---|---|---|
Set default input current limit from PSEL/OTG pins | |||||
Bit 7 | DPDM_EN | R/W | 0 | 0 – Not in D+/D– detection; 1 – Force D+/D– detection |
Default: Not in D+/D– detection (0), Back to 0 after detection complete |
Safety Timer Setting during Input DPM and Thermal Regulation | |||||
Bit 6 | TMR2X_EN | R/W | 1 | 0 – Safety timer not slowed by 2X during input DPM or thermal regulation, 1 – Safety timer slowed by 2X during input DPM or thermal regulation |
Default: Safety timer slowed by 2X (1) |
Force BATFET Off | |||||
Bit 5 | BATFET_Disable | R/W | 0 | 0 – Allow Q4 turn on, 1 – Turn off Q4 | Default: Allow Q4 turn on(0) |
Bit 4 | JEITA_VSET (45°C-60°C) | R/W | 0 | 0 – VREG, 1 – VREG_200mV | Default: VREG(0) |
Bit 3 | Reserved | R/W | 1 | 1 – Reserved. Must write "1" | |
Bit 2 | Reserved | R/W | 0 | 0 – Reserved. Must write "0" | |
Bit 1 | INT_MASK[1] | R/W | 1 | 0 – No INT during CHRG_FAULT, 1 – INT on CHRG_FAULT | Default: INT on CHRG_FAULT (1) |
Bit 0 | INT_MASK[0] | R/W | 1 | 0 – No INT during BAT_FAULT, 1 – INT on BAT_FAULT | Default: INT on BAT_FAULT (1) |