ZHCSDC8A December 2014 – November 2017
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ICHG[5] | ICHG[4] | ICHG[3] | ICHG[2] | ICHG[1] | ICHG[0] | Reserved | FORCE_20PCT |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
BIT | FIELD | TYPE | RESET | DESCRIPTION | NOTE |
---|---|---|---|---|---|
Fast Charge Current Limit | |||||
Bit 7 | ICHG[5] | R/W | 0 | 2048 mA | Offset: 512 mA Range: 512 to 4544 mA Default: 2048 mA (011000) |
Bit 6 | ICHG[4] | R/W | 1 | 1024 mA | |
Bit 5 | ICHG[3] | R/W | 1 | 512 mA | |
Bit 4 | ICHG[2] | R/W | 0 | 256 mA | |
Bit 3 | ICHG[1] | R/W | 0 | 128 mA | |
Bit 2 | ICHG[0] | R/W | 0 | 64 mA | |
Bit 1 | Reserved | R/W | 0 | 0 - Reserved | Reserved. Must write "0" |
Bit 0 | FORCE_20PCT | R/W | 0 | 0 – ICHG as REG02[7:2] programmed 1 – ICHG as 20% of REG02[7:2] programmed |
Default: ICHG as REG02[7:2] programmed (0) |