ZHCSDC8A December 2014 – November 2017
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EN_HIZ | VINDPM[3] | VINDPM[2] | VINDPM[1] | VINDPM[0] | IINLIM[2] | IINLIM[1] | IINLIM[0] |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
BIT | FIELD | TYPE | RESET | DESCRIPTION | |
---|---|---|---|---|---|
Bit 7 | EN_HIZ | R/W | 0 | 0 – Disable, 1 – Enable | Default: Disable (0) |
Input Voltage Limit | |||||
Bit 6 | VINDPM[3] | R/W | 0 | 640 mV | Offset 3.88 V, Range: 3.88 V to 5.08 V Default: 4.36 V (0110) |
Bit 5 | VINDPM[2] | R/W | 1 | 320 mV | |
Bit 4 | VINDPM[1] | R/W | 1 | 160 mV | |
Bit 3 | VINDPM[0] | R/W | 0 | 80 mV | |
Input Current Limit (Actual input current limit is the lower of I2C and ILIM) | |||||
Bit 2 | IINLIM[2] | R/W | 0 | 000 – 100 mA, 001 – 150 mA, 010 – 500 mA, 011 – 900 mA, 100 – 1.2 A, 101 – 1.5 A, 110 – 2 A, 111 – 3 A |
Default SDP: 100 mA (000)(OTG pin = 0) or 500 mA (010) (OTG pin = 1) Default DCP/CDP: 3 A (111) |
Bit 1 | IINLIM[1] | R/W | 0 | ||
Bit 0 | IINLIM[0] | R/W | 0 |