ZHCSPA6F September 2006 – January 2022
PRODUCTION DATA
To read memory without CRC generation on 32-byte page boundaries, the SKIP ROM command is followed by the READ MEMORY command, F0h, followed by the address low byte and then the address high byte.
As shown in Figure 7-4, individual bytes of address and data are transmitted LSB first.
An 8-bit CRC of the command byte and address bytes is computed by the BQ2022A and read back by the host to confirm that the correct command word and starting address were received. If the CRC read by the host is incorrect, a reset pulse must be issued and the entire sequence must be repeated. If the CRC received by the host is correct, the host issues read time slots and receives data from the BQ2022A starting at the initial address and continuing until the end of the 1024-bit data field is reached or until a reset pulse is issued. If reading occurs through the end of memory space, the host may issue eight additional read time slots and the BQ2022A responds with an 8-bit CRC of all data bytes read from the initial starting byte through the last byte of memory. After the CRC is received by the host, any subsequent read time slots appear as logical 1s until a reset pulse is issued. Any reads ended by a reset pulse prior to reaching the end of memory does not have the 8-bit CRC available.
| Initialization and SKIP ROM Command Sequence | READ MEMORY Command F0h | Address Low Byte | Address High Byte | Read and Verify CRC | Read EPROM Memory Until End of EPROM Memory | Read and Verify CRC | ||
| A0 | A7 | A8 | A15 | |||||