The WRITE STATUS command is used to program the EPROM Status data field after the BQ2022A has been issued SKIP ROM command.

The flow chart in Figure 7-7 illustrates that the host issues the WRITE STATUS command, 55h, followed by the address low byte and then the address high byte the followed by the byte of data to be programmed.

If the CRC read by the host is incorrect, a reset pulse must be issued and the entire sequence must be repeated. If the CRC received by the host is correct, the program command (5Ah) is issued. After the program command is issued, then the programming voltage, V_PP is applied to the DATA pin for period t_PROG. Prior to programming, the first seven bytes of the EPROM STATUS data field appear as logical 1s. For each bit in the data byte provided by the host that is set to a logical 0, the corresponding bit in the selected byte of the EPROM STATUS data field is programmed to a logical 0 after the programming pulse has been applied at the byte location. The eighth byte of the EPROM STATUS byte data field is factory-programmed to contain 00h.

Figure 7-7 WRITE STATUS Command Flow

After the programming pulse is applied and the data line returns to V_PU, the host issues eight read time slots to verify that the appropriate bits have been programmed. The BQ2022A responds with the data from the selected EPROM STATUS address sent least significant bit first. This response should be checked to verify the programmed byte. If the programmed byte is incorrect, then the host must reset the device and begin the write sequence again. If the BQ2022A EPROM data byte programming was successful, the BQ2022A automatically increments its address counter to select the next byte in the STATUS MEMORY data field. The least significant byte of the new two-byte address is also loaded into the 8-bit CRC generator as a starting value. The host issues the next byte of data using eight write time slots.

As the BQ2022A receives this byte of data into the RAM buffer, it also shifts the data into the CRC generator that has been preloaded with the LSB of the current address and the result is an 8-bit CRC of the new data byte and the LSB of the new address. After supplying the data byte, the host reads this 8-bit CRC from the BQ2022A with eight read time slots to confirm that the address incremented properly and the data byte was received correctly. If the CRC is incorrect, a Reset Pulse must be issued and the Write Status command sequence must be restarted. If the CRC is correct, the host issues a programming pulse and the selected byte in memory is programmed.

For both of these cases, the decision to continue programming the EPROM Status registers is made entirely by the host, because the BQ2022A is not able to determine if the 8-bit CRC calculated by the host agrees with the 8-bit CRC calculated by the BQ2022A. If an incorrect CRC is ignored and a program pulse is applied by the host, incorrect programming could occur within the BQ2022A. Also note that the BQ2022A always increments its internal address counter after the receipt of the eight read time slots used to confirm the programming of the selected EPROM byte. The decision to continue is again made entirely by the host, therefore if the EPROM data byte does not match the supplied data byte but the master continues with the WRITE STATUS command, incorrect programming could occur within the BQ2022A. The WRITE STATUS command sequence can be ended at any point by issuing a reset pulse.