SPRSPC3 February   2026 AM13E23019

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
      1.      Device Package Options
      2. 5.1.1 AM13E230x Pin Diagrams
    2. 5.2 Pin Attributes
      1. 5.2.1 Pin Attributes Header List
      2.      13
    3. 5.3 Signal Descriptions
      1.      15
      2.      16
      3.      17
      4.      18
      5.      19
      6.      20
      7.      21
      8.      22
      9.      23
      10.      24
      11.      25
      12.      26
      13.      27
      14.      28
      15.      29
      16.      30
      17.      31
      18.      32
      19.      33
      20.      34
      21.      35
      22.      36
      23.      37
      24.      38
      25.      39
      26.      40
      27.      41
      28.      42
      29.      43
      30.      44
      31.      45
      32.      46
      33.      47
      34.      48
      35.      49
      36.      50
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings – Commercial
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 Digital IO
    6. 6.6 Analog Peripherals
      1. 6.6.1 Analog-to-Digital Converter (ADC)
      2. 6.6.2 ADC Characteristics
        1. 6.6.2.1 ADC Operating Conditions
        2. 6.6.2.2 ADC Electrical Data and Timing
        3. 6.6.2.3 External ADC Start-of-Conversion Switching Characteristics
      3. 6.6.3 Comparator Subsystem (CMPSS)
      4. 6.6.4 CMPSS Electrical Data and Timing
        1. 6.6.4.1 CMPSS_LITE Comparator Electrical Characteristics
        2. 6.6.4.2 CMPSS_LITE DAC Static Electrical Characteristics
      5. 6.6.5 Programmable Gain Amplifier (PGA)
      6. 6.6.6 PGA Electrical Data and Timing
        1. 6.6.6.1 PGA Operating Conditions
        2. 6.6.6.2 PGA Characteristics
      7. 6.6.7 Temperature Sensor Characteristics
      8.      Internal Analog Connections
    7. 6.7 Control Peripherals
      1. 6.7.1 Multichannel Pulse Width Modulator (MCPWM)
      2. 6.7.2 Control Peripherals Synchronization
      3. 6.7.3 MCPWM Electrical Data and Timing
        1. 6.7.3.1 MCPWM Timing Requirements
        2. 6.7.3.2 MCPWM Switching Characteristics
      4. 6.7.4 Enhanced Capture eCAP
      5. 6.7.5 eCAP Block Diagram
      6. 6.7.6 eCAP Synchronization
      7. 6.7.7 eCAP Electrical Data and Timing
        1. 6.7.7.1 eCAP Timing Requirements
        2. 6.7.7.2 eCAP Switching Characteristics
      8. 6.7.8 Enhanced Quadrature Encoder Pulse (eQEP)
      9. 6.7.9 eQEP Electrical Data and Timing
        1. 6.7.9.1 eQEP Timing Requirements
        2. 6.7.9.2 eQEP Switching Characteristics
    8. 6.8 Communication Peripherals
      1. 6.8.1 Modular Controller Area Network (MCAN)
  8. 7 Detailed Description
    1. 7.1  Description
      1. 7.1.1 Functional Block Diagram
    2. 7.2  Memory
      1. 7.2.1 Peripheral Registers Memory Map
      2. 7.2.2 Static RAM
      3. 7.2.3 Flash Memory
    3. 7.3  Identification
    4. 7.4  Arm Cortex-M33 CPU
      1. 7.4.1 Trigonometric Math Unit (TMU)
      2. 7.4.2 Debug Subsystem
    5. 7.5  TinyEngineTM Neural-network Processing Unit (NPU)
    6. 7.6  DMA
    7. 7.7  Error Aggregator Module (EAM)
    8. 7.8  Power Management and Clock Unit (PMCU)
      1. 7.8.1 Power Management Unit (PMU)
      2. 7.8.2 Operating Modes
        1. 7.8.2.1 Functionality by Operating Mode
      3. 7.8.3 Clock Module (CKM)
    9. 7.9  UNICOMM (UART/I2C/SPI)
      1. 7.9.1 Universal Asychronous Receiver/Transmitter (UART)
      2. 7.9.2 Inter-Integrated Circuit (I2C)
      3. 7.9.3 Serial Peripheral Interface (SPI)
    10. 7.10 CAN-FD
    11. 7.11 Serial Wire Debug Interface
    12. 7.12 External Peripheral Interface (EPI)
    13. 7.13 Bootstrap Loader (BSL)
    14. 7.14 Security
      1. 7.14.1 Global Security Controller
      2. 7.14.2 AESADV
      3. 7.14.3 Keystore Controller
    15. 7.15 Timers (TIMx)
    16. 7.16 WWDT
  9. 8 Applications, Implementation, and Layout
    1. 8.1 External Oscillator
    2. 8.2 JTAG and TRACE
    3. 8.3 Application and Implementation
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Device Nomenclature
    3. 9.3 Tools and Software
    4. 9.4 Documentation Support
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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7.2.1 Peripheral Registers Memory Map

Table 7-1 Peripheral Registers Memory Map
Structure DriverLib Name Base Address
MCLK/2 Domain
EPI_REGS_GPCFG,
EPI_REGS_SDRAMCFG,
EPI_REGS_HB8CFG,
EPI_REGS_HB16CFG		 EPI0_BASE,
EPI0SDRAM_BASE,
PI0HB8_BASE,
EPI0HB16_BASE		 0x4001_A000
PGA_REGS PGA0_BASE 0x400F_C000
PGA_REGS PGA1_BASE 0x400F_D000
PGA_REGS PGA2_BASE 0x400F_E000
MCAN_REGS MCAN0_BASE 0x4011_0000
TIMG4_REGS TIMG4_BASE 0x4018_0000
TIMG12_REGS TIMG12_BASE 0x4018_8000
AES_REGS AES_BASE 0x401B_0000
CRCP_REGS CRC_BASE 0x401B_2000
KEYSTORE_REGS KEYSTORE_BASE 0x401B_6000
UNICOMMUART_REGS UC0_UART_BASE 0x4060_0000
UNICOMMUART_REGS UC1_UART_BASE 0x4060_1000
UNICOMMUART_REGS UC2_UART_BASE 0x4060_2000
UNICOMMI2CC_REGS UC0_I2CC_BASE 0x4060_8000
UNICOMMI2CC_REGS UC1_I2CC_BASE 0x4060_9000
UNICOMMI2CC_REGS UC2_I2CC_BASE 0x4060_A000
UNICOMMI2CT_REGS UC0_I2CT_BASE 0x4061_0000
UNICOMMI2CT_REGS UC1_I2CT_BASE 0x4061_1000
UNICOMMI2CT_REGS UC2_I2CT_BASE 0x4061_2000
UNICOMMSPI_REGS UC0_SPI_BASE 0x4061_8000
UNICOMMSPI_REGS UC1_SPI_BASE 0x4061_9000
UNICOMM_REGS UNICOMM0_BASE 0x4063_0000
UNICOMM_REGS UNICOMM1_BASE 0x4063_2000
UNICOMM_REGS UNICOMM2_BASE 0x4063_4000
SPG_REGS SPG0_BASE 0x4063_F000
UNICOMMUART_REGS UC3_UART_BASE 0x4064_0000
UNICOMMUART_REGS UC4_UART_BASE 0x4064_1000
UNICOMMUART_REGS UC5_UART_BASE 0x4064_2000
UNICOMMI2CC_REGS UC3_I2CC_BASE 0x4064_8000
UNICOMMI2CC_REGS UC4_I2CC_BASE 0x4064_9000
UNICOMMI2CC_REGS UC5_I2CC_BASE 0x4064_A000
UNICOMMI2CT_REGS UC3_I2CT_BASE 0x4065_0000
UNICOMMI2CT_REGS UC4_I2CT_BASE 0x4065_1000
UNICOMMI2CT_REGS UC5_I2CT_BASE 0x4065_2000
UNICOMMSPI_REGS UC3_SPI_BASE 0x4065_8000
UNICOMMSPI_REGS UC4_SPI_BASE 0x4065_9000
UNICOMM_REGS UNICOMM3_BASE 0x4067_0000
UNICOMM_REGS UNICOMM4_BASE 0x4067_2000
UNICOMM_REGS UNICOMM5_BASE 0x4067_4000
SPG_REGS SPG1_BASE 0x4067_F000
MCLK/1 Domain
ADC_LITE_REGS ADC0_BASE 0x4000_0000
ADC_LITE_REGS ADC1_BASE 0x4000_2000
ADC_LITE_REGS ADC2_BASE 0x4000_4000
ADC_LITE_RESULT_REGS ADC0RESULT_BASE 0x4000_A000
ADC_LITE_RESULT_REGS ADC1RESULT_BASE 0x4000_B000
ADC_LITE_RESULT_REGS ADC2RESULT_BASE 0x4000_C000
MCPWM_6CH_REGS MCPWM0_BASE 0x4001_0000
MCPWM_6CH_REGS MCPWM1_BASE 0x4001_1000
MCPWM_6CH_REGS MCPWM2_BASE 0x4001_2000
MCPWM_6CH_REGS MCPWM3_BASE 0x4001_3000
MCPWM_6CH_REGS MCPWM4_BASE 0x4001_4000
DMA_REGS DMA0_BASE 0x4002_0000
FLASH_CTRL_REGS FLASH_BASE 0x4002_8000
MEM_CFG_REGS MEMCFG_BASE 0x4002_A000
EAM_REGS EAM_BASE 0x4002_C000
ECAP_REGS ECAP0_BASE 0x4044_0000
ECAP_REGS ECAP1_BASE 0x4044_1000
EQEP_REGS EQEP0_BASE 0x4044_8000
EQEP_REGS EQEP1_BASE 0x4044_9000
EQEP_REGS EQEP2_BASE 0x4044_A000
CMPSS_LITE_REGS CMPSS0_BASE 0x4046_0000
CMPSS_LITE_REGS CMPSS1_BASE 0x4046_1000
CMPSS_LITE_REGS CMPSS2_BASE 0x4046_2000
CMPSS_LITE_REGS CMPSS3_BASE 0x4046_3000
INPUT_XBAR_REGS INPUTXBAR_BASE 0x4046_8000
EPWM_XBAR_REGS PWMXBAR_BASE 0x4046_9000
OUTPUTXBAR_REGS OUTPUTXBAR_BASE 0x4046_A000
SYNC_SOC_REGS SYNC_BASE 0x4046_B000
OUTPUTXBAR_FLAG_REGS OUTPUTXBAR0_FLAGS_BASE 0x4047_0000
OUTPUTXBAR_FLAG_REGS OUTPUTXBAR1_FLAGS_BASE 0x4047_1000
OUTPUTXBAR_FLAG_REGS OUTPUTXBAR2_FLAGS_BASE 0x4047_2000
OUTPUTXBAR_FLAG_REGS OUTPUTXBAR3_FLAGS_BASE 0x4047_3000
OUTPUTXBAR_FLAG_REGS OUTPUTXBAR4_FLAGS_BASE 0x4047_4000
OUTPUTXBAR_FLAG_REGS OUTPUTXBAR5_FLAGS_BASE 0x4047_5000
OUTPUTXBAR_FLAG_REGS OUTPUTXBAR6_FLAGS_BASE 0x4047_6000
OUTPUTXBAR_FLAG_REGS OUTPUTXBAR7_FLAGS_BASE 0x4047_7000
INPUT_FLAG_XBAR_REGS INPUTXBAR_FLAGS_BASE 0x4049_0000
Power Domain 0 (Always ON)
SYSCTL_REGS SYSCTL_BASE 0x400A_F000
DEBUGSS_REGS DEBUGSS_BASE 0x400C_7000
IOMUX_REGS IOMUX_BASE 0x400C_C000
WWDT_REGS WWDT_BASE 0x400D_0000
GPIO_REGS GPIO0_BASE 0x400F_0000
GPIO_REGS GPIO1_BASE 0x400F_2000
GPIO_REGS GPIO2_BASE 0x400F_4000
GPIO_REGS GPIO3_BASE 0x400F_6000
MCLK/4 Domain
NVMNW_REGS NVMNW_BASE 0x4004_2000
GSC_REGS GSC_BASE 0x4004_6000