ZHCSOP5B 数据表 | 德州仪器 TI.com.cn

ZHCSOP5B august 2021 – june 2023 AFE7900

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5.12.5 RX Typical Characteristics 3.5GHz

Typical values at T_A = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS (decimate by 6), PLL clock mode with f_REF = 491.52MHz, A_IN = –3 dBFS, DSA setting = 4 dB.

With 3.6 GHz matching, normalized to 3.6 GHz

Figure 5-137 RX In-Band Gain Flatness, f_IN = 3600 MHz

With 3.6 GHz matching
Differential Amplitude Error = P_IN(DSA Setting – 1) – P_IN(DSA Setting) + 1

Figure 5-139 RX Uncalibrated Differential Amplitude Error vs DSA Setting at 3.6 GHz

With 3.6 GHz matching
Integrated Amplitude Error = P_IN(DSA Setting) – P_IN(DSA Setting = 0) + (DSA Setting)

Figure 5-141 RX Uncalibrated Integrated Amplitude Error vs DSA Setting at 3.6 GHz

With 3.6 GHz matching
Differential Phase Error = Phase_IN(DSA Setting – 1) – Phase_IN(DSA Setting)

Figure 5-143 RX Uncalibrated Phase Error vs DSA Setting at 3.6 GHz

With 3.6 GHz matching
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0)

Figure 5-145 RX Uncalibrated Integrated Phase Error vs DSA Setting at 3.6 GHz

With 3.6 GHz matching , f_IN = 3610 MHz, A_IN = –3 dBFS

Figure 5-147 RX Output FFT at 3.6 GHz

With 3.5 GHz matching, 20-MHz tone spacing

Figure 5-149 RX IMD3 vs Input Level and Temperature at 3.6 GHz

External clock mode, 2x Decimation

Figure 5-151 RX IMD3 vs Tone Spacing at 3.76GHz

With 3.5 GHz matching, DDC bypass mode (TI only mode for characterization)

Figure 5-153 RX HD2 vs DSA Setting and Temperature at 3.6 GHz

With 3.5 GHz matching, DDC bypass mode (TI only mode for characterization)

Figure 5-155 RX HD2 vs Input Level and Temperature at 3.6 GHz

External clock mode, 25°C, 2x Decimation

Figure 5-157 RX HD2 vs Input Level

With 3.5 GHz matching, DDC bypass mode (TI only mode for characterization)

Figure 5-159 RX HD3 vs DSA Setting and Temperature at 3.6 GHz

With 3.5 GHz matching, DDC bypass mode (TI only mode for characterization)

Figure 5-161 RX HD3 vs Input Level and Temperature at 3.6 GHz

External clock mode, 25°C, 2x Decimation

Figure 5-163 RX HD3 vs Input Level

External clock mode, 25°C, 2x Decimation

Figure 5-165 RX Noise Spectral Density vs Input Level at 3.76GHz

With 3.5 GHz matching

Figure 5-167 RX SFDR Excluding HD2/3 vs DSA Setting and Channel at 3.6 GHz

External clock mode, 20MHz tone spacing, excluding 3^rd order distortion

Figure 5-169 RX 2-tone SFDR vs Input Amplitude and Frequency at 3.7 GHz

With 3.6 GHz matching, –7 dBFS each tone, 20-MHz tone spacing, all supplies at MIN, TYP, or MAX recommended operating voltages

Figure 5-171 RX IMD5 vs Supply Voltage and Channel at 3.6 GHz

With 3.6 GHz matching, normalized to phase at 25°C

Figure 5-138 RX Input Phase vs Temperature at 3.6 GHz

With 3.6 GHz matching
Differential Amplitude Error = P_IN(DSA Setting – 1) – P_IN(DSA Setting) + 1

Figure 5-140 RX Calibrated Differential Amplitude Error vs DSA Setting at 3.6 GHz

With 3.6 GHz matching
Integrated Amplitude Error = P_IN(DSA Setting) – P_IN(DSA Setting = 0) + (DSA Setting)

Figure 5-142 RX Calibrated Integrated Amplitude Error vs DSA Setting at 3.6 GHz

With 3.6 GHz matching
Differential Phase Error = Phase_IN(DSA Setting – 1) – Phase_IN(DSA Setting)

Figure 5-144 RX Calibrated Differential Phase Error vs DSA Setting at 3.6 GHz

With 3.6 GHz matching
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0)

Figure 5-146 RX Calibrated Integrated Phase Error vs DSA Setting at 3.6 GHz

With 3.5 GHz matching, each tone at –7 dBFS, 20-MHz tone spacing

Figure 5-148 RX IMD3 vs DSA Setting and Temperature at 3.6 GHz

External clock mode, 20-MHz tone spacing, 2x Decimation

Figure 5-150 RX IMD3 vs Input Level

With 3.5 GHz matching, DDC bypass mode (TI only mode for characterization)

Figure 5-152 RX HD2 vs DSA Setting and Channel at 3.6 GHz

With 3.5 GHz matching, DDC bypass mode (TI only mode for characterization)

Figure 5-154 RX HD2 vs Input Level and Channel at 3.6 GHz

External clock mode, 2x Decimation

Figure 5-156 RX HD2 vs Input Level at 3.76 GHz

With 3.5 GHz matching, DDC bypass mode (TI only mode for characterization)

Figure 5-158 RX HD3 vs DSA Setting and Channel at 3.6 GHz

With 3.5 GHz matching, DDC bypass mode (TI only mode for characterization)

Figure 5-160 RX HD3 vs Input Level and Channel at 3.6 GHz

External clock mode, 2x Decimation

Figure 5-162 RX HD3 vs Input Level at 3.76GHz

With 3.5 GHz matching, 12.5-MHz offset from tone

Figure 5-164 RX Noise Spectral Density vs Input Level and DSA Setting at 3.6 GHz

With 3.5 GHz matching

Figure 5-166 RX In-Band SFDR (±200 MHz) vs Input Level and Channel at 3.6 GHz

External clock mode, 20MHz tone spacing, excluding 3^rd order distortion

Figure 5-168 RX 2-tone SFDR vs Input Amplitude and DSA Setting at 3.7 GHz

With 3.6 GHz matching, –7 dBFS each tone, 20-MHz tone spacing, all supplies at MIN, TYP, or MAX recommended operating voltages

Figure 5-170 RX IMD3 vs Supply Voltage and Channel at 3.6 GHz

With 3.6 GHz matching, tone at –20 dBFS, 12.5-MHz offset frequency, all supplies at MIN, TYP, or MAX recommended operating voltages

Figure 5-172 RX Noise Spectral Density vs Supply Voltage and Channel at 3.6 GHz